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authorDavid Abdurachmanov <david.abdurachmanov@sifive.com>2021-06-12 17:43:57 -0700
committerPalmer Dabbelt <palmerdabbelt@google.com>2021-06-19 00:11:53 -0700
commit7ede12b01b59dc67bef2e2035297dd2da5bfe427 (patch)
treedcf04066281ea4fbbcc7db709bf462862fde2d69 /arch/riscv/boot
parent3a02764c372c50ff7917fde5c6961f6cdb81d9d5 (diff)
riscv: dts: fu740: fix cache-controller interrupts
The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/boot')
-rw-r--r--arch/riscv/boot/dts/sifive/fu740-c000.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index 8eef82e4199f..abbb960f90a0 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -273,7 +273,7 @@
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <19 20 21 22>;
+ interrupts = <19 21 22 20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {