path: root/arch/riscv/include
AgeCommit message (Expand)Author
2021-06-18riscv: Ensure BPF_JIT_REGION_START aligned with PMD sizeJisheng Zhang
2021-06-10riscv: alternative: fix typo in macro nameVitaly Wool
2021-05-22riscv: kexec: Fix W=1 build warningsJisheng Zhang
2021-05-06riscv: Consistify protect_kernel_linear_mapping_text_rodata() useGeert Uytterhoeven
2021-05-06Merge tag 'riscv-for-linus-5.13-mw0' of git:// Torvalds
2021-05-02Merge branch 'work.misc' of git:// Torvalds
2021-05-01RISC-V: Always define XIP_FIXUPPalmer Dabbelt
2021-05-01riscv: Fix 32b kernel build with CONFIG_DEBUG_VIRTUAL=yAlexandre Ghiti
2021-04-26RISC-V: enable XIPVitaly Wool
2021-04-26RISC-V: Add kdump supportNick Kossifidis
2021-04-26RISC-V: Add kexec supportNick Kossifidis
2021-04-26riscv: Constify sbi_ipi_opsJisheng Zhang
2021-04-26riscv: Constify sys_call_tableJisheng Zhang
2021-04-26riscv: Move kernel mapping outside of linear mappingAlexandre Ghiti
2021-04-26riscv: Workaround mcount name prior to clang-13Nathan Chancellor
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen
2021-04-26riscv: sifive: Add SiFive alternative portsVincent Chen
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionVincent Chen
2021-04-26riscv: Add 3 SBI wrapper functions to get cpu manufacturer informationVincent Chen
2021-04-01riscv: evaluate put_user() arg before enabling user accessBen Dooks
2021-03-27whack-a-mole: kill strlen_user() (again)Al Viro
2021-03-09riscv: process: Fix no prototype for arch_dup_task_structNanyong Sun
2021-03-09riscv: time: Fix no prototype for time_initNanyong Sun
2021-03-09riscv: ptrace: Fix no prototype warningsNanyong Sun
2021-03-09riscv: irq: Fix no prototype warningNanyong Sun
2021-03-09riscv: traps: Fix no prototype warningsNanyong Sun
2021-03-09RISC-V: correct enum sbi_ext_rfence_fidHeinrich Schuchardt
2021-03-09riscv: Add ARCH_HAS_FORTIFY_SOURCEKefeng Wang
2021-02-26Merge tag 'riscv-for-linus-5.12-mw0' of git:// Torvalds
2021-02-22riscv: Improve kasan definitionsAlexandre Ghiti
2021-02-22riscv: Remove unnecessary declarationKefeng Wang
2021-02-22RISC-V: Add a non-void return for sbi v02 functionsAtish Patra
2021-02-18RISC-V: Implement ASID allocatorAnup Patel
2021-02-18RISC-V: remove unneeded semicolonChengyang Fan
2021-02-02riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWXSebastien Van Cauwenberghe
2021-02-02riscv: virt_addr_valid must check the address belongs to linear mappingAlexandre Ghiti
2021-01-14riscv: Add dump stack in show_regsKefeng Wang
2021-01-14riscv: Enable per-task stack canariesGuo Ren
2021-01-14riscv: Add support for function error injectionGuo Ren
2021-01-14riscv: Add uprobes supportedGuo Ren
2021-01-14riscv: Add kprobes supportedGuo Ren
2021-01-14RISC-V: Implement ptrace regs and stack APIPatrick Stählin
2021-01-14riscv: Add numa support for riscv64 platformAtish Patra
2021-01-14riscv: Add support pte_protnone and pmd_protnone if CONFIG_NUMA_BALANCINGGreentime Hu
2021-01-14riscv: Separate memory init from paging initAtish Patra
2021-01-12riscv: Fixup CONFIG_GENERIC_TIME_VSYSCALLGuo Ren
2021-01-09riscv: Drop a duplicated PAGE_KERNEL_EXECKefeng Wang
2021-01-07riscv: Fix builtin DTB handlingDamien Le Moal
2021-01-07riscv: Cleanup sbi function stubs when RISCV_SBI disabledKefeng Wang