path: root/drivers/irqchip
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2021-06-17Merge tag 'irqchip-fixes-5.13-2' of ↵Thomas Gleixner
git:// into irq/urgent Pull irqchip fixes from Marc Zyngier: - Fix GICv3 NMI handling where an IRQ could be mistakenly handled as a NMI, with disatrous effects Link:
2021-06-10irqchip/gic-v3: Workaround inconsistent PMR setting on NMI entryMarc Zyngier
The arm64 entry code suffers from an annoying issue on taking a NMI, as it sets PMR to a value that actually allows IRQs to be acknowledged. This is done for consistency with other parts of the code, and is in the process of being fixed. This shouldn't be a problem, as we are not enabling interrupts whilst in NMI context. However, in the infortunate scenario that we took a spurious NMI (retired before the read of IAR) *and* that there is an IRQ pending at the same time, we'll ack the IRQ in NMI context. Too bad. In order to avoid deadlocks while running something like perf, teach the GICv3 driver about this situation: if we were in a context where no interrupt should have fired, transiently set PMR to a value that only allows NMIs before acking the pending interrupt, and restore the original value after that. This papers over the core issue for the time being, and makes NMIs great again. Sort of. Fixes: 4d6a38da8e79e94c ("arm64: entry: always set GIC_PRIO_PSR_I_SET during entry") Co-developed-by: Mark Rutland <> Signed-off-by: Mark Rutland <> Signed-off-by: Marc Zyngier <> Reviewed-by: Mark Rutland <> Link:
2021-05-16irqchip: Remove redundant error printingZhen Lei
When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot <> Signed-off-by: Zhen Lei <> Signed-off-by: Marc Zyngier <> Link:
2021-05-10irqchip/apple-aic: APPLE_AIC should depend on ARCH_APPLEGeert Uytterhoeven
The Apple Interrupt Controller is only present on Apple Silicon SoCs. Hence add a dependency on ARCH_APPLE, to prevent asking the user about this driver when configuring a kernel without Apple Silicon SoC support. Drop the default, as ARCH_APPLE already selects APPLE_AIC. Fixes: 76cde26394114f6a ("irqchip/apple-aic: Add support for the Apple Interrupt Controller") Signed-off-by: Geert Uytterhoeven <> Acked-by: Hector Martin <> Signed-off-by: Marc Zyngier <> Link:
2021-05-01Merge tag 'for-linus' of git:// Torvalds
Pull kvm updates from Paolo Bonzini: "This is a large update by KVM standards, including AMD PSP (Platform Security Processor, aka "AMD Secure Technology") and ARM CoreSight (debug and trace) changes. ARM: - CoreSight: Add support for ETE and TRBE - Stage-2 isolation for the host kernel when running in protected mode - Guest SVE support when running in nVHE mode - Force W^X hypervisor mappings in nVHE mode - ITS save/restore for guests using direct injection with GICv4.1 - nVHE panics now produce readable backtraces - Guest support for PTP using the ptp_kvm driver - Performance improvements in the S2 fault handler x86: - AMD PSP driver changes - Optimizations and cleanup of nested SVM code - AMD: Support for virtual SPEC_CTRL - Optimizations of the new MMU code: fast invalidation, zap under read lock, enable/disably dirty page logging under read lock - /dev/kvm API for AMD SEV live migration (guest API coming soon) - support SEV virtual machines sharing the same encryption context - support SGX in virtual machines - add a few more statistics - improved directed yield heuristics - Lots and lots of cleanups Generic: - Rework of MMU notifier interface, simplifying and optimizing the architecture-specific code - a handful of "Get rid of oprofile leftovers" patches - Some selftests improvements" * tag 'for-linus' of git:// (379 commits) KVM: selftests: Speed up set_memory_region_test selftests: kvm: Fix the check of return value KVM: x86: Take advantage of kvm_arch_dy_has_pending_interrupt() KVM: SVM: Skip SEV cache flush if no ASIDs have been used KVM: SVM: Remove an unnecessary prototype declaration of sev_flush_asids() KVM: SVM: Drop redundant svm_sev_enabled() helper KVM: SVM: Move SEV VMCB tracking allocation to sev.c KVM: SVM: Explicitly check max SEV ASID during sev_hardware_setup() KVM: SVM: Unconditionally invoke sev_hardware_teardown() KVM: SVM: Enable SEV/SEV-ES functionality by default (when supported) KVM: SVM: Condition sev_enabled and sev_es_enabled on CONFIG_KVM_AMD_SEV=y KVM: SVM: Append "_enabled" to module-scoped SEV/SEV-ES control variables KVM: SEV: Mask CPUID[0x8000001F].eax according to supported features KVM: SVM: Move SEV module params/variables to sev.c KVM: SVM: Disable SEV/SEV-ES if NPT is disabled KVM: SVM: Free sev_asid_bitmap during init if SEV setup fails KVM: SVM: Zero out the VMCB array used to track SEV ASID association x86/sev: Drop redundant and potentially misleading 'sev_enabled' KVM: x86: Move reverse CPUID helpers to separate header file KVM: x86: Rename GPR accessors to make mode-aware variants the defaults ...
2021-04-29Merge tag 'mips_5.13' of ↵Linus Torvalds
git:// Pull MIPS updates from Thomas Bogendoerfer: - removed get_fs/set_fs - removed broken/unmaintained MIPS KVM trap and emulate support - added support for Loongson-2K1000 - fixes and cleanups * tag 'mips_5.13' of git:// (107 commits) MIPS: BCM63XX: Use BUG_ON instead of condition followed by BUG. MIPS: select ARCH_KEEP_MEMBLOCK unconditionally mips: Do not include hi and lo in clobber list for R6 MIPS:DTS:Correct the license for Loongson-2K MIPS:DTS:Fix label name and interrupt number of ohci for Loongson-2K MIPS: Avoid handcoded DIVU in `__div64_32' altogether lib/math/test_div64: Correct the spelling of "dividend" lib/math/test_div64: Fix error message formatting mips/bootinfo:correct some comments of fw_arg MIPS: Avoid DIVU in `__div64_32' is result would be zero MIPS: Reinstate platform `__div64_32' handler div64: Correct inline documentation for `do_div' lib/math: Add a `do_div' test module MIPS: Makefile: Replace -pg with CC_FLAGS_FTRACE MIPS: pci-legacy: revert "use generic pci_enable_resources" MIPS: Loongson64: Add kexec/kdump support MIPS: pci-legacy: use generic pci_enable_resources MIPS: pci-legacy: remove busn_resource field MIPS: pci-legacy: remove redundant info messages MIPS: pci-legacy: stop using of_pci_range_to_resource ...
2021-04-26Merge tag 'arm-apple-m1-5.13' of ↵Linus Torvalds
git:// Pull ARM Apple M1 platform support from Arnd Bergmann: "The Apple M1 is the processor used it all current generation Apple Macintosh computers. Support for this platform so far is rudimentary, but it boots and can use framebuffer and serial console over a special USB cable. Support for several essential on-chip devices (USB, PCIe, IOMMU, NVMe) is work in progress but was not ready in time. A very detailed description of what works is in the commit message of commit 1bb2fd3880d4 ("Merge tag 'm1-soc-bringup-v5' [..]") and on the AsahiLinux wiki" Link: * tag 'arm-apple-m1-5.13' of git:// asm-generic/io.h: Unbork ioremap_np() declaration arm64: apple: Add initial Apple Mac mini (M1, 2020) devicetree dt-bindings: display: Add apple,simple-framebuffer arm64: Kconfig: Introduce CONFIG_ARCH_APPLE irqchip/apple-aic: Add support for the Apple Interrupt Controller dt-bindings: interrupt-controller: Add DT bindings for apple-aic arm64: Move ICH_ sysreg bits from arm-gic-v3.h to sysreg.h of/address: Add infrastructure to declare MMIO as non-posted asm-generic/io.h: implement pci_remap_cfgspace using ioremap_np arm64: Implement ioremap_np() to map MMIO as nGnRnE docs: driver-api: device-io: Document ioremap() variants & access funcs docs: driver-api: device-io: Document I/O access functions asm-generic/io.h: Add a non-posted variant of ioremap() arm64: arch_timer: Implement support for interrupt-names dt-bindings: timer: arm,arch_timer: Add interrupt-names support arm64: cputype: Add CPU implementor & types for the Apple M1 cores dt-bindings: arm: cpus: Add apple,firestorm & icestorm compatibles dt-bindings: arm: apple: Add bindings for Apple ARM platforms dt-bindings: vendor-prefixes: Add apple prefix
2021-04-24Merge tag 'irqchip-5.13' of ↵Thomas Gleixner
git:// into irq/core Pull irqchip and irqdomain updates from Marc Zyngier: New HW support: - New driver for the Nuvoton WPCM450 interrupt controller - New driver for the IDT 79rc3243x interrupt controller - Add support for interrupt trigger configuration to the MStar irqchip - Add more external interrupt support to the STM32 irqchip - Add new compatible strings for QCOM SC7280 to the qcom-pdc binding Fixes and cleanups: - Drop irq_create_strict_mappings() and irq_create_identity_mapping() from the irqdomain API, with cleanups in a couple of drivers - Fix nested NMI issue with spurious interrupts on GICv3 - Don't allow GICv4.1 vSGIs when the CPU doesn't support them - Various cleanups and minor fixes Link:
2021-04-24irqchip/xilinx: Expose Kconfig option for Zynq/ZynqMPRobert Hancock
Previously the XILINX_INTC config option was hidden and only auto-selected on the MicroBlaze platform. However, this IP can also be used on the Zynq and ZynqMP platforms as a secondary cascaded controller. Allow this option to be user-enabled on those platforms. Signed-off-by: Robert Hancock <> Signed-off-by: Marc Zyngier <> Link:
2021-04-23irqchip/gic-v3: Do not enable irqs when handling spurious interrupsHe Ying
We triggered the following error while running our 4.19 kernel with the pseudo-NMI patches backported to it: [ 14.816231] ------------[ cut here ]------------ [ 14.816231] kernel BUG at irq.c:99! [ 14.816232] Internal error: Oops - BUG: 0 [#1] SMP [ 14.816232] Process swapper/0 (pid: 0, stack limit = 0x(____ptrval____)) [ 14.816233] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G O 4.19.95.aarch64 #14 [ 14.816233] Hardware name: evb (DT) [ 14.816234] pstate: 80400085 (Nzcv daIf +PAN -UAO) [ 14.816234] pc : asm_nmi_enter+0x94/0x98 [ 14.816235] lr : asm_nmi_enter+0x18/0x98 [ 14.816235] sp : ffff000008003c50 [ 14.816235] pmr_save: 00000070 [ 14.816237] x29: ffff000008003c50 x28: ffff0000095f56c0 [ 14.816238] x27: 0000000000000000 x26: ffff000008004000 [ 14.816239] x25: 00000000015e0000 x24: ffff8008fb916000 [ 14.816240] x23: 0000000020400005 x22: ffff0000080817cc [ 14.816241] x21: ffff000008003da0 x20: 0000000000000060 [ 14.816242] x19: 00000000000003ff x18: ffffffffffffffff [ 14.816243] x17: 0000000000000008 x16: 003d090000000000 [ 14.816244] x15: ffff0000095ea6c8 x14: ffff8008fff5ab40 [ 14.816244] x13: ffff8008fff58b9d x12: 0000000000000000 [ 14.816245] x11: ffff000008c8a200 x10: 000000008e31fca5 [ 14.816246] x9 : ffff000008c8a208 x8 : 000000000000000f [ 14.816247] x7 : 0000000000000004 x6 : ffff8008fff58b9e [ 14.816248] x5 : 0000000000000000 x4 : 0000000080000000 [ 14.816249] x3 : 0000000000000000 x2 : 0000000080000000 [ 14.816250] x1 : 0000000000120000 x0 : ffff0000095f56c0 [ 14.816251] Call trace: [ 14.816251] asm_nmi_enter+0x94/0x98 [ 14.816251] el1_irq+0x8c/0x180 (IRQ C) [ 14.816252] gic_handle_irq+0xbc/0x2e4 [ 14.816252] el1_irq+0xcc/0x180 (IRQ B) [ 14.816253] arch_timer_handler_virt+0x38/0x58 [ 14.816253] handle_percpu_devid_irq+0x90/0x240 [ 14.816253] generic_handle_irq+0x34/0x50 [ 14.816254] __handle_domain_irq+0x68/0xc0 [ 14.816254] gic_handle_irq+0xf8/0x2e4 [ 14.816255] el1_irq+0xcc/0x180 (IRQ A) [ 14.816255] arch_cpu_idle+0x34/0x1c8 [ 14.816255] default_idle_call+0x24/0x44 [ 14.816256] do_idle+0x1d0/0x2c8 [ 14.816256] cpu_startup_entry+0x28/0x30 [ 14.816256] rest_init+0xb8/0xc8 [ 14.816257] start_kernel+0x4c8/0x4f4 [ 14.816257] Code: 940587f1 d5384100 b9401001 36a7fd01 (d4210000) [ 14.816258] Modules linked in: start_dp(O) smeth(O) [ 15.103092] ---[ end trace 701753956cb14aa8 ]--- [ 15.103093] Kernel panic - not syncing: Fatal exception in interrupt [ 15.103099] SMP: stopping secondary CPUs [ 15.103100] Kernel Offset: disabled [ 15.103100] CPU features: 0x36,a2400218 [ 15.103100] Memory Limit: none which is cause by a 'BUG_ON(in_nmi())' in nmi_enter(). From the call trace, we can find three interrupts (noted A, B, C above): interrupt (A) is preempted by (B), which is further interrupted by (C). Subsequent investigations show that (B) results in nmi_enter() being called, but that it actually is a spurious interrupt. Furthermore, interrupts are reenabled in the context of (B), and (C) fires with NMI priority. We end-up with a nested NMI situation, something we definitely do not want to (and cannot) handle. The bug here is that spurious interrupts should never result in any state change, and we should just return to the interrupted context. Moving the handling of spurious interrupts as early as possible in the GICv3 handler fixes this issue. Fixes: 3f1f3234bc2d ("irqchip/gic-v3: Switch to PMR masking before calling IRQ handler") Acked-by: Mark Rutland <> Signed-off-by: He Ying <> [maz: rewrote commit message, corrected Fixes: tag] Signed-off-by: Marc Zyngier <> Link: Cc:
2021-04-22irqchip: Add support for IDT 79rc3243x interrupt controllerThomas Bogendoerfer
IDT 79rc3243x SoCs have rather simple interrupt controllers connected to the MIPS CPU interrupt lines. Each of them has room for up to 32 interrupts. Signed-off-by: Thomas Bogendoerfer <> Signed-off-by: Marc Zyngier <> Link:
2021-04-22irqchip/jcore-aic: Kill use of irq_create_strict_mappings()Marc Zyngier
irq_create_strict_mappings() is a poor way to allow the use of a linear IRQ domain as a legacy one. Let's be upfront about it. Signed-off-by: Marc Zyngier <> Link:
2021-04-22irqchip/gic-v4.1: Disable vSGI upon (GIC CPUIF < v4.1) detectionLorenzo Pieralisi
GIC CPU interfaces versions predating GIC v4.1 were not built to accommodate vINTID within the vSGI range; as reported in the GIC specifications (8.2 "Changes to the CPU interface"), it is CONSTRAINED UNPREDICTABLE to deliver a vSGI to a PE with ID_AA64PFR0_EL1.GIC < b0011. Check the GIC CPUIF version by reading the SYS_ID_AA64_PFR0_EL1. Disable vSGIs if a CPUIF version < 4.1 is detected to prevent using vSGIs on systems where they may misbehave. Signed-off-by: Lorenzo Pieralisi <> Cc: Marc Zyngier <> Signed-off-by: Marc Zyngier <> Link:
2021-04-22irqchip/tb10x: Use 'fallthrough' to eliminate a warningRandy Dunlap
Use the 'fallthrough' macro to document that this switch case does indeed fall through to the next case. ../drivers/irqchip/irq-tb10x.c: In function 'tb10x_irq_set_type': ../drivers/irqchip/irq-tb10x.c:62:13: warning: this statement may fall through [-Wimplicit-fallthrough=] 62 | flow_type = IRQ_TYPE_LEVEL_LOW; ../drivers/irqchip/irq-tb10x.c:63:2: note: here 63 | case IRQ_TYPE_LEVEL_LOW: | ^~~~ Fixes: b06eb0173ef1 ("irqchip: Add TB10x interrupt controller driver") Signed-off-by: Randy Dunlap <> Cc: Thomas Gleixner <> Cc: Marc Zyngier <> Cc: Christian Ruppert <> Signed-off-by: Marc Zyngier <> Link:
2021-04-08irqchip/apple-aic: Add support for the Apple Interrupt ControllerHector Martin
This is the root interrupt controller used on Apple ARM SoCs such as the M1. This irqchip driver performs multiple functions: * Handles both IRQs and FIQs * Drives the AIC peripheral itself (which handles IRQs) * Dispatches FIQs to downstream hard-wired clients (currently the ARM timer). * Implements a virtual IPI multiplexer to funnel multiple Linux IPIs into a single hardware IPI Reviewed-by: Marc Zyngier <> Acked-by: Will Deacon <> Signed-off-by: Hector Martin <>
2021-04-08irqchip/wpcm450: Drop COMPILE_TESTMarc Zyngier
This driver is (for now) ARM specific, and currently doesn't build with a variety of architectures (ia64, RISC-V, x86_64 at the very least). Drop COMPILE_TEST from Kconfig until it gets sorted out. Reviewed-by: Jonathan Neuschäfer <> Reported-by: Stephen Rothwell <> Signed-off-by: Marc Zyngier <>
2021-04-07irqchip/irq-mst: Support polarity configurationMark-PK Tsai
Support irq polarity configuration and save and restore the config when system suspend and resume. Signed-off-by: Mark-PK Tsai <> [maz: fixed irq_set_type callback] Signed-off-by: Marc Zyngier <> Link:
2021-04-07irqchip: Add driver for WPCM450 interrupt controllerJonathan Neuschäfer
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton SoCs. The list of registers if based on the AMI vendor kernel and the Nuvoton W90N745 datasheet. Although the hardware supports other interrupt modes, the driver only supports high-level interrupts at the moment, because other modes could not be tested so far. Signed-off-by: Jonathan Neuschäfer <> Signed-off-by: Marc Zyngier <> Link:
2021-04-07irqchip/stm32: Add usart instances exti direct event supportErwan Le Ray
Add following usart instances exti direct event support (used for UART wake up). - exti 26 (USART1) is mapped to GIC 37 - exti 27 (USART2) is mapped to GIC 38 - exti 28 (USART3) is mapped to GIC 39 - exti 29 (USART6) is mapped to GIC 71 - exti 31 (UART5) is mapped to GIC 53 - exti 32 (UART7) is mapped to GIC 82 - exti 33 (UART8) is mapped to GIC 83 Signed-off-by: Erwan Le Ray <> Signed-off-by: Marc Zyngier <> Link:
2021-04-07irqchip/gic-v3: Fix OF_BAD_ADDR error handlingArnd Bergmann
When building with extra warnings enabled, clang points out a mistake in the error handling: drivers/irqchip/irq-gic-v3-mbi.c:306:21: error: result of comparison of constant 18446744073709551615 with expression of type 'phys_addr_t' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (mbi_phys_base == OF_BAD_ADDR) { Truncate the constant to the same type as the variable it gets compared to, to shut make the check work and void the warning. Fixes: 505287525c24 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller") Signed-off-by: Arnd Bergmann <> Signed-off-by: Marc Zyngier <> Link:
2021-04-07irqchip/sifive-plic: Mark two global variables __ro_after_initJisheng Zhang
All of these two are never modified after init, so they can be __ro_after_init. Signed-off-by: Jisheng Zhang <> Signed-off-by: Marc Zyngier <> Link:
2021-04-07irqchip/hisi: Use the correct HiSilicon copyrightHao Fang
s/Hisilicon/HiSilicon/ It should use capital S, according to Signed-off-by: Hao Fang <> Signed-off-by: Marc Zyngier <> Link:
2021-03-25irqchip/loongson-liointc: irqchip add 2.0 versionQing Zhang
Add IO interrupt controller support for Loongson-2K1000, different from the Loongson-3A series is that Loongson-2K1000 has 64 interrupt sources, 0-31 correspond to the device tree liointc0 device node, and the other correspond to liointc1 node. Signed-off-by: Jiaxun Yang <> Signed-off-by: Qing Zhang <> Tested-by: Ming Wang <> Acked-by: Marc Zyngier <> Signed-off-by: Thomas Bogendoerfer <>
2021-03-24irqchip/gic-v3-its: Drop the setting of PTZ altogetherShenming Lu
GICv4.1 gives a way to get the VLPI state, which needs to map the vPE first, and after the state read, we may remap the vPE back while the VPT is not empty. So we can't assume that the VPT is empty at the first map. Besides, the optimization of PTZ is probably limited since the HW should be fairly efficient to parse the empty VPT. Let's drop the setting of PTZ altogether. Signed-off-by: Shenming Lu <> Signed-off-by: Marc Zyngier <> Link:
2021-03-24irqchip/gic-v3-its: Add a cache invalidation right after vPE unmappingMarc Zyngier
In order to be able to manipulate the VPT once a vPE has been unmapped, perform the required CMO to invalidate the CPU view of the VPT. Signed-off-by: Marc Zyngier <> Signed-off-by: Shenming Lu <> Link:
2021-03-22irq: Fix typos in commentsIngo Molnar
Fix ~36 single-word typos in the IRQ, irqchip and irqdomain code comments. Signed-off-by: Ingo Molnar <> Cc: Thomas Gleixner <> Cc: Marc Zyngier <> Cc: Borislav Petkov <> Cc: Peter Zijlstra <> Cc: Signed-off-by: Ingo Molnar <>
2021-03-12MIPS: Loongson64: Move loongson_system_configuration to loongson.hQing Zhang
The purpose of separating loongson_system_configuration from boot_param.h is to keep the other structure consistent with the firmware. Signed-off-by: Jiaxun Yang <> Signed-off-by: Qing Zhang <> Acked-by: Jiaxun Yang <> Signed-off-by: Thomas Bogendoerfer <>
2021-03-09irqchip/ingenic: Add support for the JZ4760Paul Cercueil
Add support for the interrupt controller found in the JZ4760 SoC, which works exactly like the one in the JZ4770. Signed-off-by: Paul Cercueil <> Signed-off-by: Marc Zyngier <> Link:
2021-03-08irqchip: Do not blindly select CONFIG_GENERIC_IRQ_MULTI_HANDLERMarc Zyngier
Implementing CONFIG_GENERIC_IRQ_MULTI_HANDLER is a decision that is made at the architecture level, and shouldn't involve the irqchip at all (we even provide a fallback helper when the option isn't selected). Drop all instances of such selection from non-arch code. Signed-off-by: Marc Zyngier <> Link: Signed-off-by: Mark Rutland <> Tested-by: Hector Martin <> Cc: Catalin Marinas <> Cc: James Morse <> Cc: Thomas Gleixner <> Cc: Will Deacon <> Signed-off-by: Marc Zyngier <>
2021-02-15Merge tag 'irqchip-5.12' of ↵Thomas Gleixner
git:// into irq/core Pull irqchip updates from Marc Zyngier - New driver for the MIPS-based Realtek RTL838x/RTL839x SoC - Conversion of the sun6i-r support code to a hierarchical setup - Fix wake-up interrupts for the ls-extirq driver - Fix MSI allocation for the loongson-pch-msi driver - Add compatible strings for new Qualcomm SoCs - Tidy up a few Kconfig entries (IMX, CSKY) - Spelling phyksiz - Remove the sirfsoc and tango drivers Link:
2021-02-14irqchip/imx: IMX_INTMUX should not default to y, unconditionallyGeert Uytterhoeven
Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of IMX_INTMUX to ARCH_MXC, and ask the user in case of compile-testing. Fixes: 66968d7dfc3f5451 ("irqchip: Add COMPILE_TEST support for IMX_INTMUX") Signed-off-by: Geert Uytterhoeven <> Signed-off-by: Marc Zyngier <> Link:
2021-02-09irqchip/loongson-pch-msi: Use bitmap_zalloc() to allocate bitmapHuacai Chen
Currently we use bitmap_alloc() to allocate msi bitmap which should be initialized with zero. This is obviously wrong but it works because msi can fallback to legacy interrupt mode. So use bitmap_zalloc() instead. Fixes: 632dcc2c75ef6de3272aa ("irqchip: Add Loongson PCH MSI controller") Cc: Signed-off-by: Huacai Chen <> Signed-off-by: Marc Zyngier <> Link:
2021-02-04irqchip/csky-mpintc: Prevent selection on unsupported platformsGuo Ren
The irq-csky-mpintc driver is only supported on CPU_CK860 and it will generate a compilation error when selected with CPU_CK610. As it is already selected directly in the architecture Kconfig, drop the option to select it manually. Signed-off-by: Guo Ren <> [maz: rewrote commit message] Signed-off-by: Marc Zyngier <> Link:
2021-02-04irqchip: Add support for Realtek RTL838x/RTL839x interrupt controllerBert Vermeulen
This is a standard IRQ driver with only status and mask registers. The mapping from SoC interrupts (18-31) to MIPS core interrupts is done via an interrupt-map in device tree. Signed-off-by: Bert Vermeulen <> Signed-off-by: Birger Koblitz <> Acked-by: John Crispin <> Signed-off-by: Marc Zyngier <> Link:
2021-01-29irqchip/ls-extirq: add IRQCHIP_SKIP_SET_WAKE to the irqchip flagsBiwen Li
The ls-extirq driver doesn't implement the irq_set_wake() callback, while being wake-up capable. This results in ugly behaviours across suspend/resume cycles. Advertise this by adding IRQCHIP_SKIP_SET_WAKE to the irqchip flags Fixes: b16a1caf4686 ("irqchip/ls-extirq: Add LS1043A, LS1088A external interrupt support") Signed-off-by: Biwen Li <> Signed-off-by: Marc Zyngier <> Link:
2021-01-21irqchip/sun6i-r: Add wakeup supportSamuel Holland
Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them to the hardware during the syscore phase of suspend and shutdown. Then restore the original set of enabled IRQs (only the NMI) during resume. This serves two purposes. First, it lets power management firmware running on the ARISC coprocessor know which wakeup sources Linux wants to have enabled. That way, it can avoid turning them off when it shuts down the remainder of the clock tree. Second, it preconfigures the coprocessor's interrupt controller, so the firmware's wakeup logic is as simple as waiting for an interrupt to arrive. The suspend/resume logic is not conditional on PM_SLEEP because it is identical to the init/shutdown logic. Wake IRQs may be enabled during shutdown to allow powering the board back on. As an example, see commit a5c5e50cce9d ("Input: gpio-keys - add shutdown callback"). Acked-by: Maxime Ripard <> Signed-off-by: Samuel Holland <> Signed-off-by: Marc Zyngier <> Link:
2021-01-21irqchip/sun6i-r: Use a stacked irqchip driverSamuel Holland
The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the original sun4i interrupt controller than the sun7i/sun9i NMI controller. It is used for two distinct purposes: - To control the trigger, latch, and mask for the NMI input pin - To provide the interrupt input for the ARISC coprocessor As this interrupt controller is not documented, information about it comes from vendor-provided firmware blobs and from experimentation. Differences from the sun4i interrupt controller appear to be: - It only has one or two registers of each kind (max 32 or 64 IRQs) - Multiplexing logic is added to support additional inputs - There is no FIQ-related logic - There is no interrupt priority logic In order to fulfill its two purposes, this hardware block combines four types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0 pending" output from this chip, if enabled, is then routed to a SPI IRQ input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect the NMI IRQ seen at the GIC. The NMI is followed by a contiguous block of 15 "direct" (my name for them) IRQ inputs that are connected in parallel to both R_INTC and the GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the IRQs seen at the GIC. Following the direct IRQs are the ARISC's copy of banked IRQs for shared peripherals. These are not relevant to Linux. The remaining IRQs are connected to a multiplexer and provide access to the first (up to) 128 SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs. Because of the 1:1 correspondence between R_INTC and GIC inputs, this is a perfect scenario for using a stacked irqchip driver. We want to hook into setting the NMI trigger type, but not actually handle any IRQ here. To allow access to all multiplexed IRQs, this driver requires a new binding where the interrupt number matches the GIC interrupt number. (This moves the NMI from number 0 to 32 or 96, depending on the SoC.) For simplicity, copy the three-cell GIC binding; this disambiguates interrupt 0 in the old binding (the NMI) from interrupt 0 in the new binding (SPI 0) by the number of cells. Since R_INTC is in the always-on power domain, and its output is visible to the power management coprocessor, a stacked irqchip driver provides a simple way to add wakeup support to any of its IRQs. That is the next patch; for now, just the NMI is moved over. This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatible"). Acked-by: Maxime Ripard <> Signed-off-by: Samuel Holland <> Signed-off-by: Marc Zyngier <> Link:
2021-01-21irqchip/gic-v3: Fix typos in PMR/RPR SCR_EL3.FIQ handling explanationLorenzo Pieralisi
The GICv3 driver explanation related to PMR/RPR and SCR_EL3.FIQ secure/non-secure priority handling contains a couple of typos. Fix them. Signed-off-by: Lorenzo Pieralisi <> Cc: Marc Zyngier <> Signed-off-by: Marc Zyngier <> Link:
2021-01-21irqchip: Remove sirfsoc driverArnd Bergmann
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <> Signed-off-by: Arnd Bergmann <> Acked-by: Barry Song <> Signed-off-by: Marc Zyngier <> Link:
2021-01-21irqchip: Remove sigma tango driverArnd Bergmann
The tango platform is getting removed, so the driver is no longer needed. Cc: Marc Gonzalez <> Cc: Mans Rullgard <> Signed-off-by: Arnd Bergmann <> Acked-by: Mans Rullgard <> Signed-off-by: Marc Zyngier <> Link:
2021-01-12Merge tag 'irqchip-fixes-5.11-1' of ↵Thomas Gleixner
git:// into irq/urgent Pull irqchip fixes from Marc Zyngier: - Fix the MIPS CPU interrupt controller hierarchy - Simplify the PRUSS Kconfig entry - Eliminate trivial build warnings on the MIPS Loongson liointc - Fix error path in devm_platform_get_irqs_affinity() - Turn the BCM2836 IPI irq_eoi callback into irq_ack - Fix initialisation of on-stack msi_alloc_info - Cleanup spurious comma in irq-sl28cpld Link:
2021-01-10irqchip/mips-cpu: Set IPI domain parent chipMathias Kresin
Since commit 55567976629e ("genirq/irqdomain: Allow partial trimming of irq_data hierarchy") the irq_data chain is valided. The irq_domain_trim_hierarchy() function doesn't consider the irq + ipi domain hierarchy as valid, since the ipi domain has the irq domain set as parent, but the parent domain has no chip set. Hence the boot ends in a kernel panic. Set the chip for the parent domain as it is done in the mips gic irq driver, to have a valid irq_data chain. Fixes: 3838a547fda2 ("irqchip: mips-cpu: Introduce IPI IRQ domain support") Cc: <> # v5.10+ Signed-off-by: Mathias Kresin <> Signed-off-by: Marc Zyngier <> Link:
2021-01-10irqchip/pruss: Simplify the TI_PRUSS_INTC KconfigSuman Anna
The TI PRUSS INTC irqchip driver handles the local interrupt controller which is a child device of it's parent PRUSS/ICSSG device. The driver was upstreamed in parallel with the PRUSS platform driver, and was configurable independently previously. The PRUSS interrupt controller is an integral part of the overall PRUSS software architecture, and is not useful at all by itself. Simplify the TI_PRUSS_INTC Kconfig dependencies by making it silent and selected automatically when the TI_PRUSS platform driver is enabled. Signed-off-by: Suman Anna <> Reviewed-by: David Lechner <> Signed-off-by: Marc Zyngier <> Link:
2021-01-05irqchip/loongson-liointc: Fix build warningsHuacai Chen
Fix build warnings as below: >> drivers/irqchip/irq-loongson-liointc.c:134:12: warning: no previous prototype for 'liointc_of_init' [-Wmissing-prototypes] 134 | int __init liointc_of_init(struct device_node *node, | ^~~~~~~~~~~~~~~ Fixes: dbb152267908c4b2c3639492a94 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") Reported-by: kernel test robot <> Signed-off-by: Huacai Chen <> Signed-off-by: Marc Zyngier <> Link:
2020-12-20Merge tag 'for-linus' of git:// Torvalds
Pull KVM updates from Paolo Bonzini: "Much x86 work was pushed out to 5.12, but ARM more than made up for it. ARM: - PSCI relay at EL2 when "protected KVM" is enabled - New exception injection code - Simplification of AArch32 system register handling - Fix PMU accesses when no PMU is enabled - Expose CSV3 on non-Meltdown hosts - Cache hierarchy discovery fixes - PV steal-time cleanups - Allow function pointers at EL2 - Various host EL2 entry cleanups - Simplification of the EL2 vector allocation s390: - memcg accouting for s390 specific parts of kvm and gmap - selftest for diag318 - new kvm_stat for when async_pf falls back to sync x86: - Tracepoints for the new pagetable code from 5.10 - Catch VFIO and KVM irqfd events before userspace - Reporting dirty pages to userspace with a ring buffer - SEV-ES host support - Nested VMX support for wait-for-SIPI activity state - New feature flag (AVX512 FP16) - New system ioctl to report Hyper-V-compatible paravirtualization features Generic: - Selftest improvements" * tag 'for-linus' of git:// (171 commits) KVM: SVM: fix 32-bit compilation KVM: SVM: Add AP_JUMP_TABLE support in prep for AP booting KVM: SVM: Provide support to launch and run an SEV-ES guest KVM: SVM: Provide an updated VMRUN invocation for SEV-ES guests KVM: SVM: Provide support for SEV-ES vCPU loading KVM: SVM: Provide support for SEV-ES vCPU creation/loading KVM: SVM: Update ASID allocation to support SEV-ES guests KVM: SVM: Set the encryption mask for the SVM host save area KVM: SVM: Add NMI support for an SEV-ES guest KVM: SVM: Guest FPU state save/restore not needed for SEV-ES guest KVM: SVM: Do not report support for SMM for an SEV-ES guest KVM: x86: Update __get_sregs() / __set_sregs() to support SEV-ES KVM: SVM: Add support for CR8 write traps for an SEV-ES guest KVM: SVM: Add support for CR4 write traps for an SEV-ES guest KVM: SVM: Add support for CR0 write traps for an SEV-ES guest KVM: SVM: Add support for EFER write traps for an SEV-ES guest KVM: SVM: Support string IO operations for an SEV-ES guest KVM: SVM: Support MMIO for an SEV-ES guest KVM: SVM: Create trace events for VMGEXIT MSR protocol processing KVM: SVM: Create trace events for VMGEXIT processing ...
2020-12-18irqchip/bcm2836: Fix IPI acknowledgement after conversion to ↵Marc Zyngier
handle_percpu_devid_irq It appears that despite its name, the bcm2836_arm_irqchip_ipi_eoi() callback is an acknowledgement, and not an EOI. This means that we lose IPIs that are made pending between the handling of the IPI and the write to LOCAL_MAILBOX0_CLR0. With the right timing, things fail nicely. This used to work with handle_percpu_devid_fasteoi_ipi(), which started by eoi-ing the interrupt. With the standard fasteoi flow, this doesn't work anymore. So let's use this callback for what it is, an ack. Your favourite RPi-2/3 is back up and running. Fixes: ffdad793d579 ("irqchip/bcm2836: Make IPIs use handle_percpu_devid_irq()") Cc: Valentin Schneider <> Reported-by: Guenter Roeck <> Tested-by: Guenter Roeck <> Signed-off-by: Marc Zyngier <> Link:
2020-12-18irqchip/irq-sl28cpld: Convert comma to semicolonZheng Yongjun
Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun <> Signed-off-by: Marc Zyngier <> Link:
2020-12-12irqchip/qcom-pdc: Fix phantom irq when changing between rising/fallingDouglas Anderson
We have a problem if we use gpio-keys and configure wakeups such that we only want one edge to wake us up. AKA: wakeup-event-action = <EV_ACT_DEASSERTED>; wakeup-source; Specifically we end up with a phantom interrupt that blocks suspend if the line was already high and we want wakeups on rising edges (AKA we want the GPIO to go low and then high again before we wake up). The opposite is also problematic. Specifically, here's what's happening today: 1. Normally, gpio-keys configures to look for both edges. Due to the current workaround introduced in commit c3c0c2e18d94 ("pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180"), if the line was high we'd configure for falling edges. 2. At suspend time, we change to look for rising edges. 3. After qcom_pdc_gic_set_type() runs, we get a phantom interrupt. We can solve this by just clearing the phantom interrupt. NOTE: it is possible that this could cause problems for a client with very specific needs, but there's not much we can do with this hardware. As an example, let's say the interrupt signal is currently high and the client is looking for falling edges. The client now changes to look for rising edges. The client could possibly expect that if the line has a short pulse low (and back high) that it would always be detected. Specifically no matter when the pulse happened, it should either have tripped the (old) falling edge trigger or the (new) rising edge trigger. We will simply not trip it. We could narrow down the race a bit by polling our parent before changing types, but no matter what we do there will still be a period of time where we can't tell the difference between a real transition (or more than one transition) and the phantom. Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") Signed-off-by: Douglas Anderson <> Signed-off-by: Marc Zyngier <> Tested-by: Maulik Shah <> Reviewed-by: Maulik Shah <> Reviewed-by: Stephen Boyd <> Link:
2020-12-11irqchip/gic-v3-its: Flag device allocation as proxied if behind a PCI bridgeMarc Zyngier
An aliasing PCI bridge is another case where we should flag the corresponding allocation as "proxied", as MSIs are coming with the bridge's RID, and not the originating device's. Signed-off-by: Marc Zyngier <> Tested-by: John Garry <> Link:
2020-12-11irqchip/gic-v3-its: Tag ITS device as shared if allocating for a proxy deviceMarc Zyngier
The ITS already has some notion of "shared" devices. Let's map the MSI_ALLOC_FLAGS_PROXY_DEVICE flag onto this internal property. Signed-off-by: Marc Zyngier <> Tested-by: John Garry <> Link: