diff options
869 files changed, 37733 insertions, 11634 deletions
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 97fb96266344..6423377710ee 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -167,6 +167,7 @@ properties: - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC items: - enum: + - bananapi,bpi-m5 - hardkernel,odroid-c4 - hardkernel,odroid-hc4 - khadas,vim3l diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 812ae8cc5959..230b80d9d6cf 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -18,6 +18,7 @@ properties: - description: BCM2711 based Boards items: - enum: + - raspberrypi,400 - raspberrypi,4-model-b - const: brcm,bcm2711 diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e3c50f231d71..1c827c1954dc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -197,6 +197,7 @@ properties: - boundary,imx6q-nitrogen6x - compulab,cm-fx6 # CompuLab CM-FX6 - dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board + - ds,imx6q-sbc # Da Sheng COM-9XX Modules - embest,imx6q-marsboard # Embest MarS Board i.MX6Dual - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base @@ -400,6 +401,17 @@ properties: - const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM - const: fsl,imx6dl + - description: i.MX6DL based congatec QMX6 Boards + items: + - enum: + - ge,imx6dl-b105v2 # General Electric B105v2 + - ge,imx6dl-b105pv2 # General Electric B105Pv2 + - ge,imx6dl-b125v2 # General Electric B125v2 + - ge,imx6dl-b125pv2 # General Electric B125Pv2 + - ge,imx6dl-b155v2 # General Electric B155v2 + - const: congatec,qmx6 + - const: fsl,imx6dl + - description: i.MX6DL based DFI FS700-M60-6DL Board items: - const: dfi,fs700-m60-6dl @@ -685,6 +697,7 @@ properties: - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit + - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index d72e92bdf7c1..230bffeec0e5 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -17,6 +17,7 @@ properties: - items: - enum: - linksys,nslu2 + - welltech,epbx100 - const: intel,ixp42x - items: - enum: diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index aff57a8c8c30..80a05f6fee85 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -122,6 +122,10 @@ properties: - enum: - mediatek,mt8195-evb - const: mediatek,mt8195 + - description: Google Burnet (HP Chromebook x360 11MK G3 EE) + items: + - const: google,burnet + - const: mediatek,mt8183 - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) items: - enum: @@ -133,9 +137,19 @@ properties: items: - const: google,damu - const: mediatek,mt8183 - - description: Google Juniper (Acer Chromebook Spin 311) + - description: Google Fennel (Lenovo IdeaPad 3 Chromebook) + items: + - enum: + - google,fennel-sku0 + - google,fennel-sku1 + - google,fennel-sku6 + - const: google,fennel + - const: mediatek,mt8183 + - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) items: - - const: google,juniper-sku16 + - enum: + - google,juniper-sku16 + - google,juniper-sku17 - const: google,juniper - const: mediatek,mt8183 - description: Google Kakadu (ASUS Chromebook Detachable CM3) @@ -144,6 +158,10 @@ properties: - const: google,kakadu-rev2 - const: google,kakadu - const: mediatek,mt8183 + - description: Google Kappa (HP Chromebook 11a) + items: + - const: google,kappa + - const: mediatek,mt8183 - description: Google Kodama (Lenovo 10e Chromebook Tablet) items: - enum: @@ -153,6 +171,13 @@ properties: - google,kodama-sku32 - const: google,kodama - const: mediatek,mt8183 + - description: Google Willow (Acer Chromebook 311 C722/C722T) + items: + - enum: + - google,willow-sku0 + - google,willow-sku1 + - const: google,willow + - const: mediatek,mt8183 - items: - enum: - mediatek,mt8183-pumpkin diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 9b27e991bddc..9720b00c41d2 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -36,17 +36,20 @@ description: | msm8992 msm8994 msm8996 + sa8155p sc7180 sc7280 sdm630 sdm660 sdm845 sdx55 + sm8150 sm8250 sm8350 The 'board' element must be one of the following strings: + adp cdp cp01-c1 dragonboard @@ -178,6 +181,7 @@ properties: - items: - enum: - qcom,sc7280-idp + - google,senor - const: qcom,sc7280 - items: @@ -200,6 +204,16 @@ properties: - items: - enum: + - qcom,sa8155p-adp + - const: qcom,sa8155p + + - items: + - enum: + - qcom,sm8150-mtp + - const: qcom,sm8150 + + - items: + - enum: - qcom,qrb5165-rb5 - qcom,sm8250-mtp - const: qcom,sm8250 diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5fd0696a9f91..a0cce4e25039 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -302,6 +302,24 @@ properties: - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - const: renesas,r9a06g032 + - description: RZ/G2UL (R9A07G043) + items: + - enum: + - renesas,r9a07g043u11 # RZ/G2UL Type-1 + - renesas,r9a07g043u12 # RZ/G2UL Type-2 + - const: renesas,r9a07g043 + + - description: RZ/G2{L,LC} (R9A07G044) + items: + - enum: + - renesas,smarc-evk # SMARC EVK + - enum: + - renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC + - renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC + - renesas,r9a07g044l1 # Single Cortex-A55 RZ/G2L + - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L + - const: renesas,r9a07g044 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4a6f772c1043..6546b015fc62 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -600,6 +600,11 @@ properties: - const: zkmagic,a95x-z2 - const: rockchip,rk3318 + - description: Rockchip RK3568 Evaluation board + items: + - const: rockchip,rk3568-evb1-v10 + - const: rockchip,rk3568 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt deleted file mode 100644 index 3ee9b428b2f7..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt +++ /dev/null @@ -1,16 +0,0 @@ -Rockchip power-management-unit: -------------------------------- - -The pmu is used to turn off and on different power domains of the SoCs -This includes the power to the CPU cores. - -Required node properties: -- compatible value : = "rockchip,rk3066-pmu"; -- reg : physical base address and the size of the registers window - -Example: - - pmu@20004000 { - compatible = "rockchip,rk3066-pmu"; - reg = <0x20004000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml new file mode 100644 index 000000000000..53115b92d17f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Management Unit (PMU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The PMU is used to turn on and off different power domains of the SoCs. + This includes the power to the CPU cores. + +select: + properties: + compatible: + contains: + enum: + - rockchip,px30-pmu + - rockchip,rk3066-pmu + - rockchip,rk3288-pmu + - rockchip,rk3399-pmu + + required: + - compatible + +properties: + compatible: + items: + - enum: + - rockchip,px30-pmu + - rockchip,rk3066-pmu + - rockchip,rk3288-pmu + - rockchip,rk3399-pmu + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: true + +examples: + - | + pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; + reg = <0x20004000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ac750025a2eb..889128acf49a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -224,6 +224,12 @@ properties: - const: empire-electronix,m712 - const: allwinner,sun5i-a13 + - description: Forlinx OKA40i-C Development board + items: + - const: forlinx,oka40i-c + - const: forlinx,feta40i-c + - const: allwinner,sun8i-r40 + - description: FriendlyARM NanoPi A64 items: - const: friendlyarm,nanopi-a64 @@ -269,6 +275,11 @@ properties: - const: friendlyarm,nanopi-r1 - const: allwinner,sun8i-h3 + - description: FriendlyARM NanoPi R1S H5 + items: + - const: friendlyarm,nanopi-r1s-h5 + - const: allwinner,sun50i-h5 + - description: FriendlyARM ZeroPi items: - const: friendlyarm,zeropi diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 43fd2f8927d0..0afec83cc723 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -301,6 +301,33 @@ patternProperties: additionalProperties: false + core-domain: + type: object + description: | + The vast majority of hardware blocks of Tegra SoC belong to a + Core power domain, which has a dedicated voltage rail that powers + the blocks. + + properties: + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + required: - compatible - reg @@ -325,6 +352,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x7000e400 0x400>; + core-supply = <®ulator>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; @@ -338,17 +366,24 @@ examples: nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; resets = <&tegra_car 198>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt deleted file mode 100644 index ab730ea0a560..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ /dev/null @@ -1,313 +0,0 @@ -Broadcom iProc Family Clocks - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The iProc clock controller manages clocks that are common to the iProc family. -An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL, -LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL -comprises of several leaf clocks - -Required properties for a PLL and its leaf clocks: - -- compatible: - Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on -Cygnus has a compatible string of "brcm,cygnus-genpll" - -- #clock-cells: - Have a value of <1> since there are more than 1 leaf clock of a given PLL - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for the PLL - -- clocks: - The input parent clock phandle for the PLL. For most iProc PLLs, this is an -onboard crystal with a fixed rate - -- clock-output-names: - An ordered list of strings defining the names of the clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - genpll: genpll { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - -Required properties for ASIU clocks: - -ASIU clocks are a special case. These clocks are derived directly from the -reference clock of the onboard crystal - -- compatible: - Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU -clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk" - -- #clock-cells: - Have a value of <1> since there are more than 1 ASIU clocks - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for ASIU clocks - -- clocks: - The input parent clock phandle for the ASIU clock, i.e., the onboard -crystal - -- clock-output-names: - An ordered list of strings defining the names of the ASIU clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - asiu_clks: asiu_clks { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - -Cygnus ------- -PLL and leaf clock compatible strings for Cygnus are: - "brcm,cygnus-armpll" - "brcm,cygnus-genpll" - "brcm,cygnus-lcpll0" - "brcm,cygnus-mipipll" - "brcm,cygnus-asiu-clk" - "brcm,cygnus-audiopll" - -The following table defines the set of PLL/clock index and ID for Cygnus. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-cygnus.h" - - Clock Source (Parent) Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK - adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK - pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK - - genpll crystal 0 BCM_CYGNUS_GENPLL - axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK - 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK - ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK - enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK - audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK - can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK - - lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 - pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK - ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK - sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK - usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK - smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK - ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED - - mipipll crystal 0 BCM_CYGNUS_MIPIPLL - ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED - ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD - ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D - ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED - ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED - ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED - - audiopll crystal 0 BCM_CYGNUS_AUDIOPLL - ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 - ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 - ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 - -Hurricane 2 ------- -PLL and leaf clock compatible strings for Hurricane 2 are: - "brcm,hr2-armpll" - -The following table defines the set of PLL/clock for Hurricane 2: - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - -Northstar and Northstar Plus ------- -PLL and leaf clock compatible strings for Northstar and Northstar Plus are: - "brcm,nsp-armpll" - "brcm,nsp-genpll" - "brcm,nsp-lcpll0" - -The following table defines the set of PLL/clock index and ID for Northstar and -Northstar Plus. These clock IDs are defined in: - "include/dt-bindings/clock/bcm-nsp.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - genpll crystal 0 BCM_NSP_GENPLL - phy genpll 1 BCM_NSP_GENPLL_PHY_CLK - ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK - usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK - iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK - sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK - sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK - - lcpll0 crystal 0 BCM_NSP_LCPLL0 - pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK - sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK - ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK - -Northstar 2 ------------ -PLL and leaf clock compatible strings for Northstar 2 are: - "brcm,ns2-genpll-scr" - "brcm,ns2-genpll-sw" - "brcm,ns2-lcpll-ddr" - "brcm,ns2-lcpll-ports" - -The following table defines the set of PLL/clock index and ID for Northstar 2. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-ns2.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - genpll_scr crystal 0 BCM_NS2_GENPLL_SCR - scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK - fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK - audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK - ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED - ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED - ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED - - genpll_sw crystal 0 BCM_NS2_GENPLL_SW - rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK - 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK - nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK - chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK - port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK - sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK - - lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR - pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK - ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK - ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED - ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED - ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED - ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED - - lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS - wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK - rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK - ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED - ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED - ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED - ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED - -BCM63138 --------- -PLL and leaf clock compatible strings for BCM63138 are: - "brcm,bcm63138-armpll" - -Stingray ------------ -PLL and leaf clock compatible strings for Stingray are: - "brcm,sr-genpll0" - "brcm,sr-genpll1" - "brcm,sr-genpll2" - "brcm,sr-genpll3" - "brcm,sr-genpll4" - "brcm,sr-genpll5" - "brcm,sr-genpll6" - - "brcm,sr-lcpll0" - "brcm,sr-lcpll1" - "brcm,sr-lcpll-pcie" - - -The following table defines the set of PLL/clock index and ID for Stingray. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-sr.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - crmu_ref25m crystal N/A N/A - - genpll0 crystal 0 BCM_SR_GENPLL0 - clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK - clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK - clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK - clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK - clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK - clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK - - genpll1 crystal 0 BCM_SR_GENPLL1 - clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK - clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK - - genpll2 crystal 0 BCM_SR_GENPLL2 - clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK - clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK - clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK - clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK - clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK - clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK - - genpll3 crystal 0 BCM_SR_GENPLL3 - clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK - clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK - - genpll4 crystal 0 BCM_SR_GENPLL4 - clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK - clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK - clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK - clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK - clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - - genpll5 crystal 0 BCM_SR_GENPLL5 - clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK - clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK - clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK - - genpll6 crystal 0 BCM_SR_GENPLL6 - clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK - - lcpll0 crystal 0 BCM_SR_LCPLL0 - clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK - clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK - clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK - clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK - - lcpll1 crystal 0 BCM_SR_LCPLL1 - clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK - clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK - clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK - - lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE - clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml new file mode 100644 index 000000000000..8dc7b404ee12 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml @@ -0,0 +1,395 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc Family Clocks + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +description: | + The iProc clock controller manages clocks that are common to the iProc family. + An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL, + LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL + comprises of several leaf clocks + + ASIU clocks are a special case. These clocks are derived directly from the + reference clock of the onboard crystal. + +properties: + compatible: + enum: + - brcm,bcm63138-armpll + - brcm,cygnus-armpll + - brcm,cygnus-genpll + - brcm,cygnus-lcpll0 + - brcm,cygnus-mipipll + - brcm,cygnus-asiu-clk + - brcm,cygnus-audiopll + - brcm,hr2-armpll + - brcm,nsp-armpll + - brcm,nsp-genpll + - brcm,nsp-lcpll0 + - brcm,ns2-genpll-scr + - brcm,ns2-genpll-sw + - brcm,ns2-lcpll-ddr + - brcm,ns2-lcpll-ports + - brcm,sr-genpll0 + - brcm,sr-genpll1 + - brcm,sr-genpll2 + - brcm,sr-genpll3 + - brcm,sr-genpll4 + - brcm,sr-genpll5 + - brcm,sr-genpll6 + - brcm,sr-lcpll0 + - brcm,sr-lcpll1 + - brcm,sr-lcpll-pcie + + reg: + minItems: 1 + maxItems: 3 + items: + - description: base register + - description: power register + - description: ASIU or split status register + + clocks: + description: The input parent clock phandle for the PLL / ASIU clock. For + most iProc PLLs, this is an onboard crystal with a fixed rate. + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-output-names: + minItems: 1 + maxItems: 45 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,cygnus-armpll + - brcm,cygnus-genpll + - brcm,cygnus-lcpll0 + - brcm,cygnus-mipipll + - brcm,cygnus-asiu-clk + - brcm,cygnus-audiopll + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Cygnus. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-cygnus.h" + + Clock Source (Parent) Index ID + ----- --------------- ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK + adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK + pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK + + genpll crystal 0 BCM_CYGNUS_GENPLL + axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK + 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK + ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK + enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK + audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK + can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK + + lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 + pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK + ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK + sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK + usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK + smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK + ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED + + mipipll crystal 0 BCM_CYGNUS_MIPIPLL + ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED + ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD + ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D + ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED + ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED + ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED + + audiopll crystal 0 BCM_CYGNUS_AUDIOPLL + ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 + ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 + ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 + - if: + properties: + compatible: + contains: + enum: + - brcm,hr2-armpll + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock for Hurricane 2: + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + - if: + properties: + compatible: + contains: + enum: + - brcm,nsp-armpll + - brcm,nsp-genpll + - brcm,nsp-lcpll0 + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Northstar and + Northstar Plus. These clock IDs are defined in: + "include/dt-bindings/clock/bcm-nsp.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + genpll crystal 0 BCM_NSP_GENPLL + phy genpll 1 BCM_NSP_GENPLL_PHY_CLK + ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK + usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK + iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK + sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK + sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK + + lcpll0 crystal 0 BCM_NSP_LCPLL0 + pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK + sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK + ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK + - if: + properties: + compatible: + contains: + enum: + - brcm,ns2-genpll-scr + - brcm,ns2-genpll-sw + - brcm,ns2-lcpll-ddr + - brcm,ns2-lcpll-ports + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Northstar 2. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-ns2.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + genpll_scr crystal 0 BCM_NS2_GENPLL_SCR + scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK + fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK + audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK + ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED + ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED + ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED + + genpll_sw crystal 0 BCM_NS2_GENPLL_SW + rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK + 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK + nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK + chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK + port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK + sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK + + lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR + pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK + ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK + ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED + ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED + ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED + ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED + + lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS + wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK + rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK + ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED + ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED + ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED + ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + - if: + properties: + compatible: + contains: + enum: + - brcm,sr-genpll0 + - brcm,sr-genpll1 + - brcm,sr-genpll2 + - brcm,sr-genpll3 + - brcm,sr-genpll4 + - brcm,sr-genpll5 + - brcm,sr-genpll6 + - brcm,sr-lcpll0 + - brcm,sr-lcpll1 + - brcm,sr-lcpll-pcie + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Stingray. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-sr.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + crmu_ref25m crystal N/A N/A + + genpll0 crystal 0 BCM_SR_GENPLL0 + clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK + clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK + clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK + clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK + clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK + clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK + + genpll1 crystal 0 BCM_SR_GENPLL1 + clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK + clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK + + genpll2 crystal 0 BCM_SR_GENPLL2 + clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK + clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK + clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK + clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK + clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK + clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK + + genpll3 crystal 0 BCM_SR_GENPLL3 + clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK + clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK + + genpll4 crystal 0 BCM_SR_GENPLL4 + clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK + clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK + clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK + clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK + clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK + + genpll5 crystal 0 BCM_SR_GENPLL5 + clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK + clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK + clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK + + genpll6 crystal 0 BCM_SR_GENPLL6 + clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK + + lcpll0 crystal 0 BCM_SR_LCPLL0 + clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK + clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK + clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK + clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK + + lcpll1 crystal 0 BCM_SR_LCPLL1 + clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK + clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK + clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK + + lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE + clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK + - if: + properties: + compatible: + contains: + const: brcm,cygnus-genpll + then: + properties: + clock-output-names: + items: + - const: genpll + - const: axi21 + - const: 250mhz + - const: ihost_sys + - const: enet_sw + - const: audio_125 + - const: can + - if: + properties: + compatible: + contains: + const: brcm,nsp-lcpll0 + then: + properties: + clock-output-names: + items: + - const: lcpll0 + - const: pcie_phy + - const: sdio + - const: ddr_phy + - if: + properties: + compatible: + contains: + const: brcm,nsp-genpll + then: + properties: + clock-output-names: + items: + - const: genpll + - const: phy + - const: ethernetclk + - const: usbclk + - const: iprocfast + - const: sata1 + - const: sata2 + +required: + - reg + - clocks + - '#clock-cells' + - clock-output-names + +additionalProperties: false + +examples: + - | + osc1: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + genpll@301d000 { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x301d000 0x2c>, <0x301c020 0x4>; + clocks = <&os1c>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; + }; + - | + osc2: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + asiu_clks@301d048 { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x301d048 0xc>, <0x180aa024 0x4>; + clocks = <&osc2>; + clock-output-names = "keypad", "adc/touch", "pwm"; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index 9acea9d93160..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra114-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA114_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt deleted file mode 100644 index 7f02fb4ca4ad..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra124 and Tegra132 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in the header files - <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common - to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h> - (for Tegra124-specific clocks). -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. -- nvidia,external-memory-controller : phandle of the EMC driver. - -The node should contain a "emc-timings" subnode for each supported RAM type (see -field RAM_CODE in register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set - is used for. - -Each "emc-timings" node should contain a "timing" subnode for every supported -EMC clock rate. - -Required properties for "timing" nodes : -- clock-frequency : Should contain the memory clock rate to which this timing -relates. -- nvidia,parent-clock-frequency : Should contain the rate at which the current -parent of the EMC clock should be running at this timing. -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - emc-parent : the clock that should be the parent of the EMC clock at this -timing. - -Example SoC include file: - -/ { - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA124_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <112400000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; - - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml new file mode 100644 index 000000000000..ec7ab1483652 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + const: nvidia,tegra124-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + + nvidia,external-memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the external memory controller node + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that + this timing set is used for + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + external memory clock rate in Hz + minimum: 1000000 + maximum: 1000000000 + + nvidia,parent-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + rate of parent clock in Hz + minimum: 1000000 + maximum: 1000000000 + + clocks: + items: + - description: parent clock of EMC + + clock-names: + items: + - const: emc-parent + + required: + - clock-frequency + - nvidia,parent-clock-frequency + - clocks + - clock-names + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra124-car.h> + + car: clock-controller@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb-controller@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + clocks = <&car TEGRA124_CLK_USB2>; + resets = <&car TEGRA124_CLK_USB2>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted file mode 100644 index 6c5901b503d0..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra20 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra20-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra20-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA20_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml new file mode 100644 index 000000000000..459d2a525393 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + enum: + - nvidia,tegra20-car + - nvidia,tegra30-car + - nvidia,tegra114-car + - nvidia,tegra210-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + + car: clock-controller@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb-controller@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + clocks = <&car TEGRA20_CLK_USB2>; + resets = <&car TEGRA20_CLK_USB2>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt deleted file mode 100644 index 26f237f641b7..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt +++ /dev/null @@ -1,56 +0,0 @@ -NVIDIA Tegra210 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra210-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra210-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra210-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA210_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt deleted file mode 100644 index 63618cde12df..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra30 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra30-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra30-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA30_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index e747d73687cb..a7333ad938d2 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -12,6 +12,7 @@ Required properties: * "qcom,scm-ipq4019" * "qcom,scm-ipq806x" * "qcom,scm-ipq8074" + * "qcom,scm-mdm9607" * "qcom,scm-msm8660" * "qcom,scm-msm8916" * "qcom,scm-msm8960" diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index 96c914e048f5..2015f50aed0f 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -73,7 +73,7 @@ i2c0: i2c@f8034600 { pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; wm8731: wm8731@1a { compatible = "wm8731"; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9d27aa5111d4..1181b590db71 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -54,8 +54,14 @@ properties: - const: arm,mmu-500 - description: NVIDIA SoCs that program two ARM MMU-500s identically items: + - description: NVIDIA SoCs that require memory controller interaction + and may program multiple ARM MMU-500s identically with the memory + controller interleaving translations between multiple instances + for improved performance. + items: - enum: - - nvidia,tegra194-smmu + - const: nvidia,tegra194-smmu + - const: nvidia,tegra186-smmu - const: nvidia,smmu-500 - items: - const: arm,mmu-500 @@ -165,10 +171,11 @@ allOf: contains: enum: - nvidia,tegra194-smmu + - nvidia,tegra186-smmu then: properties: reg: - minItems: 2 + minItems: 1 maxItems: 2 else: properties: diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 19c7bd482a51..d3f05d5934d5 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -52,10 +52,11 @@ properties: - description: MAC RX clock - description: For MPU family, used for power mode - description: For MPU family, used for PHY without quartz + - description: PTP clock clock-names: minItems: 3 - maxItems: 5 + maxItems: 6 contains: enum: - stmmaceth @@ -63,6 +64,7 @@ properties: - mac-clk-rx - ethstp - eth-ck + - ptp_ref st,syscon: $ref: "/schemas/types.yaml#/definitions/phandle-array" diff --git a/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml new file mode 100644 index 000000000000..debfb54a8042 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx PCI controller + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: PCI host controller found in the Intel IXP4xx SoC series. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + items: + - enum: + - intel,ixp42x-pci + - intel,ixp43x-pci + description: The two supported variants are ixp42x and ixp43x, + though more variants may exist. + + reg: + items: + - description: IXP4xx-specific registers + + interrupts: + items: + - description: Main PCI interrupt + - description: PCI DMA interrupt 1 + - description: PCI DMA interrupt 2 + + ranges: + maxItems: 2 + description: Typically one memory range of 64MB and one IO + space range of 64KB. + + dma-ranges: + maxItems: 1 + description: The DMA range tells the PCI host which addresses + the RAM is at. It can map only 64MB so if the RAM is bigger + than 64MB the DMA access has to be restricted to these + addresses. + + "#interrupt-cells": true + + interrupt-map: true + + interrupt-map-mask: + items: + - const: 0xf800 + - const: 0 + - const: 0 + - const: 7 + +required: + - compatible + - reg + - dma-ranges + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + pci@c0000000 { + compatible = "intel,ixp43x-pci"; + reg = <0xc0000000 0x1000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + + ranges = + <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, + <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; + dma-ranges = + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ + <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */ + <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */ + <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */ + <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */ + }; diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt index 8c60e6985950..5ffd0f55d010 100644 --- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt @@ -42,22 +42,22 @@ Required properties (child nodes): Examples: - cpm_comphy: phy@120000 { + CP11X_LABEL(comphy): phy@120000 { compatible = "marvell,comphy-cp110"; reg = <0x120000 0x6000>; - marvell,system-controller = <&cpm_syscon0>; - clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, - <&CP110_LABEL(clk) 1 18>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, + <&CP11X_LABEL(clk) 1 18>; clock-names = "mg_clk", "mg_core_clk", "axi_clk"; #address-cells = <1>; #size-cells = <0>; - cpm_comphy0: phy@0 { + CP11X_LABEL(comphy0): phy@0 { reg = <0>; #phy-cells = <1>; }; - cpm_comphy1: phy@1 { + CP11X_LABEL(comphy1): phy@1 { reg = <1>; #phy-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml index a5b027a6e70f..5bebd86bf8b6 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml @@ -30,9 +30,6 @@ properties: "#clock-cells": const: 0 - "#phy-cells": - const: 0 - clocks: maxItems: 1 @@ -120,7 +117,6 @@ required: - reg - clock-output-names - "#clock-cells" - - "#phy-cells" - host-port - otg-port @@ -131,26 +127,25 @@ examples: #include <dt-bindings/clock/rk3399-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> - u2phy0: usb2-phy@e450 { + u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; clocks = <&cru SCLK_USB2PHY0_REF>; clock-names = "phyclk"; clock-output-names = "clk_usbphy0_480m"; #clock-cells = <0>; - #phy-cells = <0>; u2phy0_host: host-port { - #phy-cells = <0>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "linestate"; + #phy-cells = <0>; }; u2phy0_otg: otg-port { - #phy-cells = <0>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "otg-bvalid", "otg-id", "linestate"; + #phy-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index a96e6dbf1858..01bdda167eef 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -25,7 +25,9 @@ properties: compatible: enum: - fsl,imx7d-gpc + - fsl,imx8mn-gpc - fsl,imx8mq-gpc + - fsl,imx8mm-gpc reg: maxItems: 1 @@ -54,6 +56,7 @@ properties: Power domain index. Valid values are defined in include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc + include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc maxItems: 1 clocks: @@ -66,6 +69,16 @@ properties: power-supply: true + resets: + description: | + A number of phandles to resets that need to be asserted during + power-up sequencing of the domain. The resets belong to devices + located inside the power domain, which need to be held in reset + across the power-up sequence. So no means to specify what each + reset is in a generic power-domain binding. + minItems: 1 + maxItems: 4 + required: - '#power-domain-cells' - reg diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index ff21bfef8204..4807b560f00d 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,mdm9607-rpmpd - qcom,msm8916-rpmpd - qcom,msm8939-rpmpd - qcom,msm8976-rpmpd @@ -26,6 +27,7 @@ properties: - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sc7280-rpmhpd + - qcom,sc8180x-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sm8150-rpmhpd diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml new file mode 100644 index 000000000000..84ddc772b003 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas RZ/G2L System Controller (SYSC) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The RZ/G2L System Controller (SYSC) performs system control of the LSI and + supports following functions, + - External terminal state capture function + - 34-bit address space access function + - Low power consumption control + - WDT stop control + +properties: + compatible: + enum: + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + + reg: + maxItems: 1 + + interrupts: + items: + - description: CA55/CM33 Sleep/Software Standby Mode request interrupt + - description: CA55 Software Standby Mode release request interrupt + - description: CM33 Software Standby Mode release request interrupt + - description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt + + interrupt-names: + items: + - const: lpm_int + - const: ca55stbydone_int + - const: cm33stbyr_int + - const: ca55_deny + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0x11020000 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", + "ca55_deny"; + }; diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml new file mode 100644 index 000000000000..9b9d71087466 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Domains + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + Rockchip processors include support for multiple power domains + which can be powered up/down by software based on different + application scenarios to save power. + + Power domains contained within power-controller node are + generic power domain providers documented in + Documentation/devicetree/bindings/power/power-domain.yaml. + + IP cores belonging to a power domain should contain a + "power-domains" property that is a phandle for the + power domain node representing the domain. + +properties: + $nodename: + const: power-controller + + compatible: + enum: + - rockchip,px30-power-controller + - rockchip,rk3036-power-controller + - rockchip,rk3066-power-controller + - rockchip,rk3128-power-controller + - rockchip,rk3188-power-controller + - rockchip,rk3228-power-controller + - rockchip,rk3288-power-controller + - rockchip,rk3328-power-controller + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller + + "#power-domain-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - "#power-domain-cells" + +additionalProperties: false + +patternProperties: + "^power-domain@[0-9a-f]+$": + + $ref: "#/$defs/pd-node" + + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^power-domain@[0-9a-f]+$": + + $ref: "#/$defs/pd-node" + + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^power-domain@[0-9a-f]+$": + + $ref: "#/$defs/pd-node" + + unevaluatedProperties: false + + properties: + "#power-domain-cells": + const: 0 + +$defs: + pd-node: + type: object + description: | + Represents the power domains within the power controller node. + + properties: + reg: + maxItems: 1 + description: | + Power domain index. Valid values are defined in + "include/dt-bindings/power/px30-power.h" + "include/dt-bindings/power/rk3036-power.h" + "include/dt-bindings/power/rk3066-power.h" + "include/dt-bindings/power/rk3128-power.h" + "include/dt-bindings/power/rk3188-power.h" + "include/dt-bindings/power/rk3228-power.h" + "include/dt-bindings/power/rk3288-power.h" + "include/dt-bindings/power/rk3328-power.h" + "include/dt-bindings/power/rk3366-power.h" + "include/dt-bindings/power/rk3368-power.h" + "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" + + clocks: + minItems: 1 + maxItems: 30 + description: | + A number of phandles to clocks that need to be enabled + while power domain switches state. + + pm_qos: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + "#power-domain-cells": + enum: [0, 1] + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + required: + - reg + - "#power-domain-cells" + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/power/rk3399-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + qos_hdcp: qos@ffa90000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + power-management@ff310000 { + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; + + power-controller { + compatible = "rockchip,rk3399-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_CENTER */ + power-domain@RK3399_PD_IEP { + reg = <RK3399_PD_IEP>; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_RGA { + reg = <RK3399_PD_RGA>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VCODEC { + reg = <RK3399_PD_VCODEC>; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VDU { + reg = <RK3399_PD_VDU>; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VIO { + reg = <RK3399_PD_VIO>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3399_PD_HDCP { + reg = <RK3399_PD_HDCP>; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 54a7700df08f..800d511502c4 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -25,6 +25,9 @@ properties: - const: allwinner,sun8i-a83t-pwm - const: allwinner,sun8i-h3-pwm - items: + - const: allwinner,sun8i-v3s-pwm + - const: allwinner,sun7i-a20-pwm + - items: - const: allwinner,sun50i-a64-pwm - const: allwinner,sun5i-a13-pwm - items: diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..370579aeeca1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund <steen.hegelund@microchip.com> + - Lars Povlsen <lars.povlsen@microchip.com> + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + items: + - description: global control block registers + + reg-names: + items: + - const: gcb + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + - cpu-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@11010008 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + diff --git a/Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml b/Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml new file mode 100644 index 000000000000..61963fa9347e --- /dev/null +++ b/Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/intel,ixp46x-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP46x RNG bindings + +description: | + The Intel IXP46x has a random number generator at a fixed physical + location in memory. Each read is guaranteed to provide a unique + 32 bit random number. + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + compatible: + const: intel,ixp46x-rng + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rng@70002100 { + compatible = "intel,ixp46x-rng"; + reg = <0x70002100 4>; + }; + diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index 8051c17e640e..d74a7a5ae9f2 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -27,6 +27,7 @@ Required properties in pwrap device node. "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs "mediatek,mt8183-pwrap" for MT8183 SoCs + "mediatek,mt8195-pwrap" for MT8195 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs - interrupts: IRQ for pwrap in SOC - reg-names: Must include the following entries: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 2684f22a1d85..d511f01fcac6 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -32,12 +32,14 @@ properties: enum: - qcom,rpm-apq8084 - qcom,rpm-ipq6018 + - qcom,rpm-msm8226 - qcom,rpm-msm8916 - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8996 - qcom,rpm-msm8998 - qcom,rpm-sdm660 + - qcom,rpm-sm6125 - qcom,rpm-qcs404 qcom,smd-channels: diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt deleted file mode 100644 index f96511aa3897..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip General Register Files (GRF) - -The general register file will be used to do static set by software, which -is composed of many registers for system control. - -From RK3368 SoCs, the GRF is divided into two sections, -- GRF, used for general non-secure system, -- SGRF, used for general secure system, -- PMUGRF, used for always on system - -On RK3328 SoCs, the GRF adds a section for USB2PHYGRF, - -ON RK3308 SoC, the GRF is divided into four sections: -- GRF, used for general non-secure system, -- SGRF, used for general secure system, -- DETECTGRF, used for audio codec system, -- COREGRF, used for pvtm, - -Required Properties: - -- compatible: GRF should be one of the following: - - "rockchip,px30-grf", "syscon": for px30 - - "rockchip,rk3036-grf", "syscon": for rk3036 - - "rockchip,rk3066-grf", "syscon": for rk3066 - - "rockchip,rk3188-grf", "syscon": for rk3188 - - "rockchip,rk3228-grf", "syscon": for rk3228 - - "rockchip,rk3288-grf", "syscon": for rk3288 - - "rockchip,rk3308-grf", "syscon": for rk3308 - - "rockchip,rk3328-grf", "syscon": for rk3328 - - "rockchip,rk3368-grf", "syscon": for rk3368 - - "rockchip,rk3399-grf", "syscon": for rk3399 - - "rockchip,rv1108-grf", "syscon": for rv1108 -- compatible: DETECTGRF should be one of the following: - - "rockchip,rk3308-detect-grf", "syscon": for rk3308 -- compatilbe: COREGRF should be one of the following: - - "rockchip,rk3308-core-grf", "syscon": for rk3308 -- compatible: PMUGRF should be one of the following: - - "rockchip,px30-pmugrf", "syscon": for px30 - - "rockchip,rk3368-pmugrf", "syscon": for rk3368 - - "rockchip,rk3399-pmugrf", "syscon": for rk3399 -- compatible: SGRF should be one of the following: - - "rockchip,rk3288-sgrf", "syscon": for rk3288 -- compatible: USB2PHYGRF should be one of the following: - - "rockchip,px30-usb2phy-grf", "syscon": for px30 - - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328 -- compatible: USBGRF should be one of the following: - - "rockchip,rv1108-usbgrf", "syscon": for rv1108 -- reg: physical base address of the controller and length of memory mapped - region. - -Example: GRF and PMUGRF of RK3399 SoCs - - pmugrf: syscon@ff320000 { - compatible = "rockchip,rk3399-pmugrf", "syscon"; - reg = <0x0 0xff320000 0x0 0x1000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; - reg = <0x0 0xff770000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml new file mode 100644 index 000000000000..62fa72cfea34 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/rockchip/grf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip General Register Files (GRF) + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + oneOf: + - items: + - enum: + - rockchip,rk3288-sgrf + - rockchip,rv1108-pmugrf + - rockchip,rv1108-usbgrf + - const: syscon + - items: + - enum: + - rockchip,px30-grf + - rockchip,px30-pmugrf + - rockchip,px30-usb2phy-grf + - rockchip,rk3036-grf + - rockchip,rk3066-grf + - rockchip,rk3188-grf + - rockchip,rk3228-grf + - rockchip,rk3288-grf + - rockchip,rk3308-core-grf + - rockchip,rk3308-detect-grf + - rockchip,rk3308-grf + - rockchip,rk3308-usb2phy-grf + - rockchip,rk3328-grf + - rockchip,rk3328-usb2phy-grf + - rockchip,rk3368-grf + - rockchip,rk3368-pmugrf + - rockchip,rk3399-grf + - rockchip,rk3399-pmugrf + - rockchip,rk3568-grf + - rockchip,rk3568-pmugrf + - rockchip,rv1108-grf + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-grf + + then: + properties: + lvds: + description: + Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt + + - if: + properties: + compatible: + contains: + const: rockchip,rk3288-grf + + then: + properties: + edp-phy: + description: + Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3066-grf + - rockchip,rk3188-grf + - rockchip,rk3288-grf + + then: + properties: + usbphy: + type: object + + $ref: "/schemas/phy/rockchip-usb-phy.yaml#" + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: rockchip,rk3328-grf + + then: + properties: + gpio: + type: object + + $ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#" + + unevaluatedProperties: false + + power-controller: + type: object + + $ref: "/schemas/power/rockchip,power-controller.yaml#" + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: rockchip,rk3399-grf + + then: + properties: + mipi-dphy-rx0: + type: object + + $ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#" + + unevaluatedProperties: false + + pcie-phy: + description: + Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt + + patternProperties: + "phy@[0-9a-f]+$": + description: + Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt + + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-pmugrf + - rockchip,rk3036-grf + - rockchip,rk3308-grf + - rockchip,rk3368-pmugrf + + then: + properties: + reboot-mode: + type: object + + $ref: "/schemas/power/reset/syscon-reboot-mode.yaml#" + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-usb2phy-grf + - rockchip,rk3228-grf + - rockchip,rk3308-usb2phy-grf + - rockchip,rk3328-usb2phy-grf + - rockchip,rk3399-grf + - rockchip,rv1108-grf + + then: + required: + - "#address-cells" + - "#size-cells" + + patternProperties: + "usb2phy@[0-9a-f]+$": + type: object + + $ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#" + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-pmugrf + - rockchip,px30-grf + - rockchip,rk3228-grf + - rockchip,rk3288-grf + - rockchip,rk3328-grf + - rockchip,rk3368-pmugrf + - rockchip,rk3368-grf + - rockchip,rk3399-pmugrf + - rockchip,rk3399-grf + + then: + properties: + io-domains: + description: + Documentation/devicetree/bindings/power/rockchip-io-domain.txt + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/rk3399-power.h> + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + reg = <0xff770000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy-rx0"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + }; + + u2phy0: usb2phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "linestate"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt deleted file mode 100644 index 8304eceb62e4..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ /dev/null @@ -1,136 +0,0 @@ -* Rockchip Power Domains - -Rockchip processors include support for multiple power domains which can be -powered up/down by software based on different application scenes to save power. - -Required properties for power domain controller: -- compatible: Should be one of the following. - "rockchip,px30-power-controller" - for PX30 SoCs. - "rockchip,rk3036-power-controller" - for RK3036 SoCs. - "rockchip,rk3066-power-controller" - for RK3066 SoCs. - "rockchip,rk3128-power-controller" - for RK3128 SoCs. - "rockchip,rk3188-power-controller" - for RK3188 SoCs. - "rockchip,rk3228-power-controller" - for RK3228 SoCs. - "rockchip,rk3288-power-controller" - for RK3288 SoCs. - "rockchip,rk3328-power-controller" - for RK3328 SoCs. - "rockchip,rk3366-power-controller" - for RK3366 SoCs. - "rockchip,rk3368-power-controller" - for RK3368 SoCs. - "rockchip,rk3399-power-controller" - for RK3399 SoCs. -- #power-domain-cells: Number of cells in a power-domain specifier. - Should be 1 for multiple PM domains. -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- reg: index of the power domain, should use macros in: - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. -- clocks (optional): phandles to clocks which need to be enabled while power domain - switches state. -- pm_qos (optional): phandles to qos blocks which need to be saved and restored - while power domain switches state. - -Qos Example: - - qos_gpu: qos_gpu@ffaf0000 { - compatible ="syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - -Example: - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu { - reg = <RK3288_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - - power: power-controller { - compatible = "rockchip,rk3368-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu_1 { - reg = <RK3368_PD_GPU_1>; - clocks = <&cru ACLK_GPU_CFG>; - }; - }; - -Example 2: - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VIO>; - - pd_vo { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VO>; - - pd_vopb { - reg = <RK3399_PD_VOPB>; - }; - - pd_vopl { - reg = <RK3399_PD_VOPL>; - }; - }; - }; - }; - -Node of a device using power domains must have a power-domains property, -containing a phandle to the power device node and an index specifying which -power domain to use. -The index should use macros in: - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. - -Example of the node using power domain: - - node { - /* ... */ - power-domains = <&power RK3288_PD_GPU>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3368_PD_GPU_1>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3399_PD_VOPB>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index a16e37b01e1d..39b66e9ce3e3 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -20,6 +20,9 @@ properties: - const: allwinner,sun6i-a31-i2s - const: allwinner,sun8i-a83t-i2s - const: allwinner,sun8i-h3-i2s + - items: + - const: allwinner,sun8i-v3-i2s + - const: allwinner,sun8i-h3-i2s - const: allwinner,sun50i-a64-codec-i2s - items: - const: allwinner,sun50i-a64-i2s diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml index 9718358826ab..26eca21e1f0f 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml @@ -12,12 +12,15 @@ maintainers: properties: compatible: - enum: + oneOf: # FIXME: This is documented in the PRCM binding, but needs to be # migrated here at some point # - allwinner,sun8i-a23-codec-analog - - allwinner,sun8i-h3-codec-analog - - allwinner,sun8i-v3s-codec-analog + - const: allwinner,sun8i-h3-codec-analog + - items: + - const: allwinner,sun8i-v3-codec-analog + - const: allwinner,sun8i-h3-codec-analog + - const: allwinner,sun8i-v3s-codec-analog reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml new file mode 100644 index 000000000000..a35da257b070 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 Thermal Sensor + +maintainers: + - Dmitry Osipenko <digetx@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + TSENSOR provides thermal and voltage sensors which monitor temperature + and voltage of the chip. Sensors are placed across the die to gauge the + temperature of the whole chip. The TSENSOR module: + + Generates an interrupt to SW to lower temperature via DVFS on reaching + a certain thermal/voltage threshold. + + Generates a signal to the CAR to reduce CPU frequency by half on reaching + a certain thermal/voltage threshold. + + Generates a signal to the PMC when the temperature reaches dangerously high + levels to reset the chip and sets a flag in the PMC. + + TSENSOR has two channels which monitor two different spots of the SoC. + +properties: + compatible: + const: nvidia,tegra30-tsensor + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + assigned-clock-parents: true + assigned-clock-rates: true + assigned-clocks: true + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + thermal-sensor@70014000 { + compatible = "nvidia,tegra30-tsensor"; + reg = <0x70014000 0x500>; + interrupts = <0 102 4>; + clocks = <&clk 100>; + resets = <&rst 100>; + + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0b3b6af7bd5b..4a2eaf28e3fd 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -46,6 +46,8 @@ properties: - qcom,msm8996-tsens - qcom,msm8998-tsens - qcom,sc7180-tsens + - qcom,sc7280-tsens + - qcom,sc8180x-tsens - qcom,sdm845-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt deleted file mode 100644 index 7f94669e9ebe..000000000000 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt +++ /dev/null @@ -1,85 +0,0 @@ -* Temperature Sensor ADC (TSADC) on rockchip SoCs - -Required properties: -- compatible : should be "rockchip,<name>-tsadc" - "rockchip,px30-tsadc": found on PX30 SoCs - "rockchip,rv1108-tsadc": found on RV1108 SoCs - "rockchip,rk3228-tsadc": found on RK3228 SoCs - "rockchip,rk3288-tsadc": found on RK3288 SoCs - "rockchip,rk3328-tsadc": found on RK3328 SoCs - "rockchip,rk3368-tsadc": found on RK3368 SoCs - "rockchip,rk3399-tsadc": found on RK3399 SoCs -- reg : physical base address of the controller and length of memory mapped - region. -- interrupts : The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the name "tsadc-apb". -- pinctrl-names : The pin control state names; -- pinctrl-0 : The "init" pinctrl state, it will be set before device probe. -- pinctrl-1 : The "default" pinctrl state, it will be set after reset the - TSADC controller. -- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend. -- #thermal-sensor-cells : Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. - -Optional properties: -- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. -- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. -- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW - 1:HIGH. -- rockchip,grf : The phandle of the syscon node for the general register file. - -Exiample: -tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -Example: referring to thermal sensors: -thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml new file mode 100644 index 000000000000..b96ea277b558 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/rockchip-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Temperature Sensor ADC (TSADC) on Rockchip SoCs + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,px30-tsadc # PX30 SoCs + - rockchip,rv1108-tsadc # RV1108 SoCs + - rockchip,rk3228-tsadc # RK3228 SoCs + - rockchip,rk3288-tsadc # RK3288 SoCs + - rockchip,rk3328-tsadc # RK3328 SoCs + - rockchip,rk3368-tsadc # RK3368 SoCs + - rockchip,rk3399-tsadc # RK3399 SoCs + - rockchip,rk3568-tsadc # RK3568 SoCs + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: tsadc + - const: apb_pclk + + resets: + maxItems: 1 + + reset-names: + items: + - const: tsadc-apb + + "#thermal-sensor-cells": + const: 1 + + rockchip,grf: + description: The phandle of the syscon node for the general register file. + $ref: /schemas/types.yaml#/definitions/phandle + + rockchip,hw-tshut-temp: + description: The hardware-controlled shutdown temperature value. + $ref: /schemas/types.yaml#/definitions/uint32 + + rockchip,hw-tshut-mode: + description: The hardware-controlled shutdown mode 0:CRU 1:GPIO. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + rockchip,hw-tshut-polarity: + description: The hardware-controlled active polarity 0:LOW 1:HIGH. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/rk3288-cru.h> + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3288-tsadc"; + reg = <0xff280000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + }; diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml index 1c7cf32e7ac2..53fd24bdc34e 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -12,11 +12,18 @@ maintainers: properties: compatible: - enum: - - allwinner,sun4i-a10-timer - - allwinner,sun8i-a23-timer - - allwinner,sun8i-v3s-timer - - allwinner,suniv-f1c100s-timer + oneOf: + - enum: + - allwinner,sun4i-a10-timer + - allwinner,sun8i-a23-timer + - allwinner,sun8i-v3s-timer + - allwinner,suniv-f1c100s-timer + - items: + - enum: + - allwinner,sun50i-a64-timer + - allwinner,sun50i-h6-timer + - allwinner,sun50i-h616-timer + - const: allwinner,sun8i-a23-timer reg: maxItems: 1 @@ -34,8 +41,8 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun4i-a10-timer + enum: + - allwinner,sun4i-a10-timer then: properties: @@ -46,8 +53,8 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun8i-a23-timer + enum: + - allwinner,sun8i-a23-timer then: properties: @@ -58,20 +65,9 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun8i-v3s-timer - - then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - - if: - properties: - compatible: - items: - const: allwinner,suniv-f1c100s-timer + enum: + - allwinner,sun8i-v3s-timer + - allwinner,suniv-f1c100s-timer then: properties: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2bbc27aae977..07fb0d25fc15 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -249,6 +249,8 @@ patternProperties: description: Colorful GRP, Shenzhen Xueyushi Technology Ltd. "^compulab,.*": description: CompuLab Ltd. + "^congatec,.*": + description: congatec GmbH "^coreriver,.*": description: CORERIVER Semiconductor Co.,Ltd. "^corpro,.*": @@ -315,6 +317,8 @@ patternProperties: description: DPTechnics "^dragino,.*": description: Dragino Technology Co., Limited + "^ds,.*": + description: DaSheng, Inc. "^dserve,.*": description: dServe Technology B.V. "^dynaimage,.*": @@ -409,6 +413,8 @@ patternProperties: description: Firefly "^focaltech,.*": description: FocalTech Systems Co.,Ltd + "^forlinx,.*": + description: Baoding Forlinx Embedded Technology Co., Ltd. "^frida,.*": description: Shenzhen Frida LCD Co., Ltd. "^friendlyarm,.*": @@ -1252,6 +1258,8 @@ patternProperties: description: Western Digital Corp. "^we,.*": description: Würth Elektronik GmbH. + "^welltech,.*": + description: Welltech Computer Co., Limited. "^wetek,.*": description: WeTek Electronics, limited. "^wexler,.*": diff --git a/MAINTAINERS b/MAINTAINERS index b80e6f70156b..f52954ab7ec9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1850,6 +1850,7 @@ F: Documentation/devicetree/bindings/arm/gemini.txt F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt +F: arch/arm/boot/dts/gemini* F: arch/arm/mach-gemini/ F: drivers/crypto/gemini/ F: drivers/net/ethernet/cortina/ @@ -2210,6 +2211,7 @@ M: Daniel Palmer <daniel@thingy.jp> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ +T: git git://github.com/linux-chenxing/linux.git F: Documentation/devicetree/bindings/arm/mstar/* F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml @@ -2479,9 +2481,12 @@ F: drivers/*/*/*s3c24* F: drivers/*/*s3c24* F: drivers/*/*s3c64xx* F: drivers/*/*s5pv210* +F: drivers/clocksource/samsung_pwm_timer.c F: drivers/memory/samsung/ +F: drivers/pwm/pwm-samsung.c F: drivers/soc/samsung/ F: drivers/tty/serial/samsung* +F: include/clocksource/samsung_pwm.h F: include/linux/platform_data/*s3c* F: include/linux/serial_s3c.h F: include/linux/soc/samsung/ @@ -7177,6 +7182,13 @@ F: include/linux/firewire.h F: include/uapi/linux/firewire*.h F: tools/firewire/ +FIRMWARE FRAMEWORK FOR ARMV8-A +M: Sudeep Holla <sudeep.holla@arm.com> +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: drivers/firmware/arm_ffa/ +F: include/linux/arm_ffa.h + FIRMWARE LOADER (request_firmware) M: Luis Chamberlain <mcgrof@kernel.org> L: linux-kernel@vger.kernel.org @@ -9381,6 +9393,7 @@ F: include/linux/soc/ixp4xx/qmgr.h INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT M: Deepak Saxena <dsaxena@plexity.net> S: Maintained +F: Documentation/devicetree/bindings/display/intel,ixp46x-rng.yaml F: drivers/char/hw_random/ixp4xx-rng.c INTEL KEEM BAY DRM DRIVER @@ -11941,6 +11954,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git F: Documentation/devicetree/bindings/memory-controllers/ F: drivers/memory/ F: include/dt-bindings/memory/ +F: include/memory/ MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA M: Dmitry Osipenko <digetx@gmail.com> @@ -13510,12 +13524,6 @@ L: linux-omap@vger.kernel.org S: Maintained F: arch/arm/mach-omap2/omap_hwmod*data* -OMAP HWMOD DATA FOR OMAP4-BASED DEVICES -M: Benoît Cousson <bcousson@baylibre.com> -L: linux-omap@vger.kernel.org -S: Maintained -F: arch/arm/mach-omap2/omap_hwmod_44xx_data.c - OMAP HWMOD SUPPORT M: Benoît Cousson <bcousson@baylibre.com> M: Paul Walmsley <paul@pwsan.com> @@ -14179,6 +14187,12 @@ S: Maintained F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml F: drivers/pci/controller/dwc/pcie-fu740.c +PCI DRIVER FOR INTEL IXP4XX +M: Linus Walleij <linus.walleij@linaro.org> +S: Maintained +F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml +F: drivers/pci/controller/pci-ixp4xx.c + PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) M: Jonathan Derrick <jonathan.derrick@intel.com> L: linux-pci@vger.kernel.org @@ -18126,6 +18140,7 @@ F: include/media/i2c/tw9910.h TEE SUBSYSTEM M: Jens Wiklander <jens.wiklander@linaro.org> +R: Sumit Garg <sumit.garg@linaro.org> L: op-tee@lists.trustedfirmware.org S: Maintained F: Documentation/staging/tee.rst @@ -129,6 +129,11 @@ endif $(if $(word 2, $(KBUILD_EXTMOD)), \ $(error building multiple external modules is not supported)) +# Remove trailing slashes +ifneq ($(filter %/, $(KBUILD_EXTMOD)),) +KBUILD_EXTMOD := $(shell dirname $(KBUILD_EXTMOD).) +endif + export KBUILD_EXTMOD # Kbuild will save output files in the current working directory. @@ -544,14 +549,21 @@ scripts_basic: $(Q)rm -f .tmp_quiet_recordmcount PHONY += outputmakefile +ifdef building_out_of_srctree # Before starting out-of-tree build, make sure the source tree is clean. # outputmakefile generates a Makefile in the output directory, if using a # separate output directory. This allows convenient use of make in the # output directory. # At the same time when output Makefile generated, generate .gitignore to # ignore whole output directory + +quiet_cmd_makefile = GEN Makefile + cmd_makefile = { \ + echo "\# Automatically generated by $(srctree)/Makefile: don't edit"; \ + echo "include $(srctree)/Makefile"; \ + } > Makefile + outputmakefile: -ifdef building_out_of_srctree $(Q)if [ -f $(srctree)/.config -o \ -d $(srctree)/include/config -o \ -d $(srctree)/arch/$(SRCARCH)/include/generated ]; then \ @@ -562,7 +574,7 @@ ifdef building_out_of_srctree false; \ fi $(Q)ln -fsn $(srctree) source - $(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile $(srctree) + $(call cmd,makefile) $(Q)test -e .gitignore || \ { echo "# this is build directory, ignore it"; echo "*"; } > .gitignore endif @@ -658,7 +670,7 @@ endif ifeq ($(KBUILD_EXTMOD),) # Objects we will link into vmlinux / subdirs we need to visit -core-y := init/ usr/ +core-y := init/ usr/ arch/$(SRCARCH)/ drivers-y := drivers/ sound/ drivers-$(CONFIG_SAMPLES) += samples/ drivers-$(CONFIG_NET) += net/ @@ -961,8 +973,8 @@ KBUILD_CFLAGS += $(CC_FLAGS_CFI) export CC_FLAGS_CFI endif -ifdef CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B -KBUILD_CFLAGS += -falign-functions=32 +ifdef CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B +KBUILD_CFLAGS += -falign-functions=64 endif # arch Makefile may override CC so keep this after arch Makefile is included @@ -1089,41 +1101,6 @@ export INSTALL_DTBS_PATH ?= $(INSTALL_PATH)/dtbs/$(KERNELRELEASE) MODLIB = $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE) export MODLIB -HOST_LIBELF_LIBS = $(shell pkg-config libelf --libs 2>/dev/null || echo -lelf) - -has_libelf = $(call try-run,\ - echo "int main() {}" | $(HOSTCC) $(KBUILD_HOSTLDFLAGS) -xc -o /dev/null $(HOST_LIBELF_LIBS) -,1,0) - -ifdef CONFIG_STACK_VALIDATION - ifeq ($(has_libelf),1) - objtool_target := tools/objtool FORCE - else - SKIP_STACK_VALIDATION := 1 - export SKIP_STACK_VALIDATION - endif -endif - -PHONY += resolve_btfids_clean - -resolve_btfids_O = $(abspath $(objtree))/tools/bpf/resolve_btfids - -# tools/bpf/resolve_btfids directory might not exist -# in output directory, skip its clean in that case -resolve_btfids_clean: -ifneq ($(wildcard $(resolve_btfids_O)),) - $(Q)$(MAKE) -sC $(srctree)/tools/bpf/resolve_btfids O=$(resolve_btfids_O) clean -endif - -ifdef CONFIG_BPF -ifdef CONFIG_DEBUG_INFO_BTF - ifeq ($(has_libelf),1) - resolve_btfids_target := tools/bpf/resolve_btfids FORCE - else - ERROR_RESOLVE_BTFIDS := 1 - endif -endif # CONFIG_DEBUG_INFO_BTF -endif # CONFIG_BPF - PHONY += prepare0 export extmod_prefix = $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD)/) @@ -1235,7 +1212,7 @@ prepare0: archprepare $(Q)$(MAKE) $(build)=. # All the preparing.. -prepare: prepare0 prepare-objtool prepare-resolve_btfids +prepare: prepare0 PHONY += remove-stale-files remove-stale-files: @@ -1252,26 +1229,6 @@ uapi-asm-generic: $(Q)$(MAKE) $(asm-generic)=arch/$(SRCARCH)/include/generated/uapi/asm \ generic=include/uapi/asm-generic -PHONY += prepare-objtool prepare-resolve_btfids -prepare-objtool: $(objtool_target) -ifeq ($(SKIP_STACK_VALIDATION),1) -ifdef CONFIG_FTRACE_MCOUNT_USE_OBJTOOL - @echo "error: Cannot generate __mcount_loc for CONFIG_DYNAMIC_FTRACE=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2 - @false -endif -ifdef CONFIG_UNWINDER_ORC - @echo "error: Cannot generate ORC metadata for CONFIG_UNWINDER_ORC=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2 - @false -else - @echo "warning: Cannot use CONFIG_STACK_VALIDATION=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2 -endif -endif - -prepare-resolve_btfids: $(resolve_btfids_target) -ifeq ($(ERROR_RESOLVE_BTFIDS),1) - @echo "error: Cannot resolve BTF IDs for CONFIG_DEBUG_INFO_BTF, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2 - @false -endif # Generate some files # --------------------------------------------------------------------------- @@ -1360,6 +1317,43 @@ scripts_unifdef: scripts_basic $(Q)$(MAKE) $(build)=scripts scripts/unifdef # --------------------------------------------------------------------------- +# Tools + +ifdef CONFIG_STACK_VALIDATION +prepare: tools/objtool +endif + +ifdef CONFIG_BPF +ifdef CONFIG_DEBUG_INFO_BTF +prepare: tools/bpf/resolve_btfids +endif +endif + +PHONY += resolve_btfids_clean + +resolve_btfids_O = $(abspath $(objtree))/tools/bpf/resolve_btfids + +# tools/bpf/resolve_btfids directory might not exist +# in output directory, skip its clean in that case +resolve_btfids_clean: +ifneq ($(wildcard $(resolve_btfids_O)),) + $(Q)$(MAKE) -sC $(srctree)/tools/bpf/resolve_btfids O=$(resolve_btfids_O) clean +endif + +# Clear a bunch of variables before executing the submake +ifeq ($(quiet),silent_) +tools_silent=s +endif + +tools/: FORCE + $(Q)mkdir -p $(objtree)/tools + $(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/ + +tools/%: FORCE + $(Q)mkdir -p $(objtree)/tools + $(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/ $* + +# --------------------------------------------------------------------------- # Kernel selftest PHONY += kselftest @@ -1959,20 +1953,6 @@ kernelversion: image_name: @echo $(KBUILD_IMAGE) -# Clear a bunch of variables before executing the submake - -ifeq ($(quiet),silent_) -tools_silent=s -endif - -tools/: FORCE - $(Q)mkdir -p $(objtree)/tools - $(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/ - -tools/%: FORCE - $(Q)mkdir -p $(objtree)/tools - $(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/ $* - quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))) cmd_rmfiles = rm -rf $(rm-files) diff --git a/arch/alpha/Kbuild b/arch/alpha/Kbuild new file mode 100644 index 000000000000..c2302017403a --- /dev/null +++ b/arch/alpha/Kbuild @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ +obj-$(CONFIG_MATHEMU) += math-emu/ diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile index c2946431d88d..52529ee42dac 100644 --- a/arch/alpha/Makefile +++ b/arch/alpha/Makefile @@ -38,8 +38,6 @@ KBUILD_CFLAGS += $(cflags-y) -Wa,-mev6 head-y := arch/alpha/kernel/head.o -core-y += arch/alpha/kernel/ arch/alpha/mm/ -core-$(CONFIG_MATHEMU) += arch/alpha/math-emu/ libs-y += arch/alpha/lib/ # export what is needed by arch/alpha/boot/Makefile diff --git a/arch/arc/Makefile b/arch/arc/Makefile index e47adc97a89b..c0d87ac2e221 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -85,9 +85,6 @@ KBUILD_LDFLAGS += $(ldflags-y) head-y := arch/arc/kernel/head.o -# See arch/arc/Kbuild for content of core part of the kernel -core-y += arch/arc/ - # w/o this dtb won't embed into kernel binary core-y += arch/arc/boot/dts/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 06b6187b67af..3ea1c417339f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -394,7 +394,8 @@ config ARCH_IXP4XX select HAVE_PCI select IXP4XX_IRQ select IXP4XX_TIMER - select NEED_MACH_IO_H + # With the new PCI driver this is not needed + select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO help diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 7902bc2096e0..1c4384db223d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -609,6 +609,14 @@ choice when u-boot hands over to the kernel, the system silently crashes, with no serial output at all. + config DEBUG_MSTARV7_PMUART + bool "Kernel low-level debugging messages via MSTARV7 PM UART" + depends on ARCH_MSTARV7 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + for MSTAR ARMv7-based platforms on PM UART. + config DEBUG_MT6589_UART0 bool "Mediatek mt6589 UART0" depends on ARCH_MEDIATEK @@ -1607,6 +1615,7 @@ config DEBUG_UART_PHYS default 0x18000400 if DEBUG_BCM_HR2 default 0x18023000 if DEBUG_BCM_IPROC_UART3 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 + default 0x1f221000 if DEBUG_MSTARV7_PMUART default 0x20001000 if DEBUG_HIP01_UART default 0x20060000 if DEBUG_RK29_UART0 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 @@ -1724,6 +1733,7 @@ config DEBUG_UART_VIRT default 0xf0100000 if DEBUG_DIGICOLOR_UA0 default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836 + default 0xf0221000 if DEBUG_MSTARV7_PMUART default 0xf1000300 if DEBUG_BCM_5301X default 0xf1000400 if DEBUG_BCM_HR2 default 0xf1002000 if DEBUG_MT8127_UART0 @@ -1805,8 +1815,8 @@ config DEBUG_UART_VIRT default 0xfedc0000 if DEBUG_EP93XX default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART - default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN - default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN + default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN + default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 @@ -1829,6 +1839,7 @@ config DEBUG_UART_8250_SHIFT default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \ DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \ DEBUG_OMAP7XXUART3 + default 3 if DEBUG_MSTARV7_PMUART default 2 config DEBUG_UART_8250_WORD diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 415c3514573a..173da685a52e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -252,7 +252,6 @@ endif export TEXT_OFFSET GZFLAGS MMUEXT -core-y += arch/arm/ # If we have a machine-specific directory, then include it in the build. core-y += $(machdirs) $(platdirs) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e7..863347b6b65e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ + bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2835-rpi-zero.dtb \ bcm2835-rpi-zero-w.dtb @@ -240,6 +241,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorcp.dtb dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-welltech-epbx100.dtb \ intel-ixp43x-gateworks-gw2358.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ @@ -513,8 +515,14 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ + imx6dl-b105pv2.dtb \ + imx6dl-b105v2.dtb \ + imx6dl-b125v2.dtb \ + imx6dl-b125pv2.dtb \ + imx6dl-b155v2.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ imx6q-gw52xx.dtb \ @@ -725,7 +733,8 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-ts4600.dtb \ - imx28-tx28.dtb + imx28-tx28.dtb \ + imx28-xea.dtb dtb-$(CONFIG_ARCH_NOMADIK) += \ ste-nomadik-s8815.dtb \ ste-nomadik-nhk15.dtb @@ -1234,6 +1243,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ @@ -1415,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb-a1.dtb \ aspeed-ast2600-evb.dtb \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-ampere-mtjade.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 3ea286180382..1103a2cb836f 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -393,10 +393,10 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; -&gpio3 { +&gpio3_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 86cad9912906..80116646a3fe 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -101,7 +101,7 @@ }; &gpio3 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 69acaf4ea0f3..0afcc2ee0b63 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -436,7 +436,7 @@ }; &gpio3 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 7615327d906a..74db0fc39397 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -101,7 +101,7 @@ }; &gpio1 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; output-high; @@ -118,7 +118,7 @@ /* an external pulldown on U21 pin 4. */ &gpio3 { - bt_aud_in { + bt-aud-in-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 36d963db4026..688e14e82eba 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -333,7 +333,7 @@ status = "okay"; &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; @@ -496,7 +496,7 @@ status = "okay"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; /* WLS1271 WiFi */ wlcore: wlcore@1 { compatible = "ti,wl1271"; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 902e295b309e..9cf39c93defb 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -495,7 +495,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index d5f8d5e2eb5d..001657be0381 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -510,7 +510,7 @@ &epwmss2 { status = "okay"; - ecap2: ecap@100 { + ecap2: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; @@ -646,7 +646,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e923d065304d..5e598ac96dcc 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -458,14 +458,14 @@ }; &gpio3 { - p4 { + pr1-mii-ctl-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_HIGH>; output-high; line-name = "PR1_MII_CTRL"; }; - p10 { + mux-mii-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 4e90f9c23d2e..8121a199607c 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -150,7 +150,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index 98d8ed4ad967..39e5d2ce600a 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -353,7 +353,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index f841afb27844..5403e47c07e2 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -25,10 +25,6 @@ regulator-always-on; }; -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - &mmc2 { vmmc-supply = <&vmmcsd_fixed>; pinctrl-names = "default"; @@ -37,68 +33,6 @@ status = "okay"; }; -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; - - flash_enable: flash-enable { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ - >; - }; - - imu_interrupt: imu-interrupt { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ - >; - }; - - ethernet_interrupt: ethernet-interrupt{ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; -}; - &lcdc { status = "okay"; @@ -167,10 +101,6 @@ }; }; -&rtc { - system-power-controller; -}; - &mcasp0 { #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -267,6 +197,66 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + flash_enable: flash-enable { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + >; + }; + + imu_interrupt: imu-interrupt { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + >; + }; + + ethernet_interrupt: ethernet-interrupt{ + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + user_leds_s0: user-leds-s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ @@ -427,6 +417,7 @@ &mmc1 { status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; @@ -434,6 +425,7 @@ }; &rtc { + system-power-controller; clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 1eaa26533466..2bfe60d32783 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -140,14 +140,14 @@ }; &gpio1 { - hmtc_rst { + hmtc-rst-hog { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; output-high; line-name = "homematic_reset"; }; - hmtc_prog { + hmtc-prog-hog { gpio-hog; gpios = <27 GPIO_ACTIVE_LOW>; output-high; @@ -156,14 +156,14 @@ }; &gpio3 { - zgb_rst { + zgb-rst-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_LOW>; output-low; line-name = "zigbee_reset"; }; - zgb_boot { + zgb-boot-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 039a9ab4c7ea..859e760df4c8 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1486,7 +1486,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; @@ -1789,7 +1789,7 @@ }; }; - target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ + gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0xae000 0x4>, <0xae010 0x4>, @@ -1995,15 +1995,12 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap0: pwm@100 { + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <31>; - interrupt-names = "ecap0"; status = "disabled"; }; @@ -2017,8 +2014,7 @@ }; ehrpwm0: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -2056,15 +2052,12 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap1: pwm@100 { + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <47>; - interrupt-names = "ecap1"; status = "disabled"; }; @@ -2078,8 +2071,7 @@ }; ehrpwm1: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -2117,15 +2109,12 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap2: pwm@100 { + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <61>; - interrupt-names = "ecap2"; status = "disabled"; }; @@ -2139,8 +2128,7 @@ }; ehrpwm2: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 6e4d05d649e9..e2677682b540 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -786,7 +786,7 @@ pinctrl-0 = <&gpio0_pins>; status = "okay"; - p23 { + sel-emmc-nand-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; /* SelEMMCorNAND selects between eMMC and NAND: @@ -813,13 +813,16 @@ status = "okay"; }; +&gpio5_target { + ti,no-reset-on-init; +}; + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&display_mux_pins>; status = "okay"; - ti,no-reset-on-init; - p8 { + sel-lcd-hdmi-hog { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e217ffc09770..40ef3973f2a9 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -194,7 +194,7 @@ ranges = <0x0 0x9000 0x1000>; uart0: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -712,7 +712,7 @@ ranges = <0x0 0x22000 0x1000>; uart1: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -740,7 +740,7 @@ ranges = <0x0 0x24000 0x1000>; uart2: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1168,7 +1168,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; @@ -1399,7 +1399,7 @@ ranges = <0x0 0xa6000 0x1000>; uart3: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1427,7 +1427,7 @@ ranges = <0x0 0xa8000 0x1000>; uart4: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1455,7 +1455,7 @@ ranges = <0x0 0xaa000 0x1000>; uart5: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1747,10 +1747,9 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1760,8 +1759,7 @@ ehrpwm0: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -1799,10 +1797,9 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1812,8 +1809,7 @@ ehrpwm1: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -1851,10 +1847,9 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1864,8 +1859,7 @@ ehrpwm2: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; @@ -1905,8 +1899,7 @@ ehrpwm3: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; @@ -1946,8 +1939,7 @@ ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; @@ -1987,8 +1979,7 @@ ehrpwm5: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; @@ -2070,7 +2061,7 @@ }; }; - target-module@22000 { /* 0x48322000, ap 116 64.0 */ + gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x22000 0x4>, <0x22010 0x4>, diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index f517d1e843cf..aae0af10a5b1 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -725,7 +725,7 @@ pinctrl-0 = <&display_mux_pins>; status = "okay"; - p1 { + sel-lcd-hdmi-hog { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI @@ -860,7 +860,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_default>; pinctrl-1 = <&spi0_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &spi1 { @@ -868,7 +868,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_default>; pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &usb2_phy1 { diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi index ebf4d3cc1cfb..6d7530a48c73 100644 --- a/arch/arm/boot/dts/am5718.dtsi +++ b/arch/arm/boot/dts/am5718.dtsi @@ -17,17 +17,13 @@ * VCP1, VCP2 * MLB * ISS - * USB3, USB4 + * USB3 */ &usb3_tm { status = "disabled"; }; -&usb4_tm { - status = "disabled"; -}; - &atl_tm { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 0d5fe2bfb683..aed81568a297 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -454,20 +454,20 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; @@ -610,12 +610,11 @@ >; }; -&gpio3 { - status = "okay"; +&gpio3_target { ti,no-reset-on-init; }; -&gpio2 { +&gpio2_target { status = "okay"; ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 8bec21ed0de5..583a241f1151 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -13,7 +13,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts new file mode 100644 index 000000000000..dd7148060c4a --- /dev/null +++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 IBM Corp. + +#include "aspeed-ast2600-evb.dts" + +/ { + model = "AST2600 A1 EVB"; + + /delete-node/regulator-vcc-sdhci0; + /delete-node/regulator-vcc-sdhci1; + /delete-node/regulator-vccq-sdhci0; + /delete-node/regulator-vccq-sdhci1; +}; + +/delete-node/ &sdc; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 2772796e215e..b7eb552640cb 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> / { model = "AST2600 EVB"; @@ -21,6 +22,46 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + vcc_sdhci0: regulator-vcc-sdhci0 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci0: regulator-vccq-sdhci0 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; + + vcc_sdhci1: regulator-vcc-sdhci1 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci1: regulator-vccq-sdhci1 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; }; &mdio0 { @@ -107,7 +148,8 @@ &emmc { non-removable; bus-width = <4>; - max-frequency = <52000000>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; }; &rtc { @@ -121,37 +163,7 @@ m25p,fast-read; label = "bmc"; spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x2000000>; // 32MB - label = "rofs"; - }; - - rwfs@6000000 { - reg = <0x2a00000 0x1600000>; // 22MB - label = "rwfs"; - }; - }; +#include "openbmc-flash-layout-64.dtsi" }; }; @@ -245,3 +257,46 @@ &uhci { status = "okay"; }; + +&sdc { + status = "okay"; +}; + +/* + * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be + * toggled by GPIO pins. + * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the + * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to + * a 1.8v and a 3.3v power load switch that provides signal voltage to + * sdhci0 bus. + * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled. + * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal + * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled, + * sdhci0 signal voltage becomes 1.8v. + * AST2600-A2 EVB also supports toggling signal voltage for sdhci1. + * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3 + * as power-switch-gpio. + */ +&sdhci0 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci0>; + vqmmc-supply = <&vccq_sdhci0>; + clk-phase-sd-hs = <7>, <200>; +}; + +&sdhci1 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci1>; + vqmmc-supply = <&vccq_sdhci1>; + clk-phase-sd-hs = <7>, <200>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 6aeb47c44eba..79d17841b3d7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -34,7 +34,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 8f5ec22e51c2..57b0c45a2298 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -9,7 +9,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { @@ -110,6 +110,30 @@ linux,code = <ASPEED_GPIO(Q, 5)>; }; + psu1_vin_good { + label = "PSU1_VIN_GOOD"; + gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 4)>; + }; + + psu2_vin_good { + label = "PSU2_VIN_GOOD"; + gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 5)>; + }; + + psu1_present { + label = "PSU1_PRESENT"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(I, 0)>; + }; + + psu2_present { + label = "PSU2_PRESENT"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(I, 1)>; + }; + }; gpioA0mux: mux-controller { @@ -280,7 +304,7 @@ m25p,fast-read; label = "bmc"; /* spi-max-frequency = <50000000>; */ -#include "openbmc-flash-layout.dtsi" +#include "openbmc-flash-layout-64.dtsi" }; }; @@ -332,6 +356,16 @@ status = "okay"; }; +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + &mac1 { status = "okay"; pinctrl-names = "default"; @@ -426,6 +460,19 @@ status = "okay"; }; +&i2c10 { + status = "okay"; + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + }; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + &gfx { status = "okay"; memory-region = <&gfx_memory>; @@ -529,8 +576,9 @@ "S1_DDR_SAVE","","", /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","", "","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","", + /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", + /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", + "","","","","", /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", "","","","", /*K0-K7*/ "","","","","","","","", @@ -540,7 +588,8 @@ /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","", /*Q0-Q7*/ "","","","","","UID_BUTTON","","", - /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","", + /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", + "OCP_MAIN_PWREN","RESET_BUTTON","","", /*S0-S7*/ "","","","","","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts index c2ece0b91885..3395de96ee11 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index 2c29ac037d32..7c6af7f226e7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index dcab6e78dfa4..33e413ca07e4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -15,7 +15,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 5ef88c377358..01dace8f5e5f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -55,7 +55,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 2fb8b147f489..90a3f485c67a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -280,7 +280,7 @@ chosen { stdout-path = &uart1; - bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk"; + bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon"; }; ast-adc-hwmon { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 7b4b2b126ad8..b6b16356f571 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -37,7 +37,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 3295c8c7c05c..d26a9e16ff7c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -202,6 +202,35 @@ linux,code = <12>; }; }; + + leds { + compatible = "gpio-leds"; + + /* RTC battery fault LED at the back */ + led-rtc-battery { + gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; + }; + + /* BMC Card fault LED at the back */ + led-bmc { + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure Identify LED at the back */ + led-rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure fault LED at the back */ + led-rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + + /* PCIE slot power LED */ + led-pcieslot-power { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; + }; + }; }; &gpio0 { @@ -214,7 +243,7 @@ /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", "PIN_HOLE_RESET_OUT_N","","","","", /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", + /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", @@ -222,7 +251,7 @@ /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", + /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","", /*S0-S7*/ "","","","","","","","", @@ -353,10 +382,47 @@ &i2c1 { status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + + power-supply@68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; - pca2: pca9552@61 { + power-supply@69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + power-supply@6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +}; + +&i2c4 { + status = "okay"; + + pca2: pca9552@65 { compatible = "nxp,pca9552"; - reg = <0x61>; + reg = <0x65>; #address-cells = <1>; #size-cells = <0>; @@ -424,12 +490,222 @@ reg = <9>; type = <PCA955X_TYPE_GPIO>; }; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c4mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c01: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c01-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c01-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; + + i2c4mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c02: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c02-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c02-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; + + i2c4mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca_cable_card_c03: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c03-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c03-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; }; +}; + +&i2c5 { + status = "okay"; - pca3: pca9552@62 { + pca3: pca9552@66 { compatible = "nxp,pca9552"; - reg = <0x62>; + reg = <0x66>; #address-cells = <1>; #size-cells = <0>; @@ -512,44 +788,6 @@ }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - power-supply@68 { - compatible = "ibm,cffps"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps"; - reg = <0x69>; - }; - - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; -}; - -&i2c4 { - status = "okay"; - i2c-switch@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -558,56 +796,69 @@ status = "okay"; i2c-mux-idle-disconnect; - i2c4mux0chn0: i2c@0 { + i2c5mux0chn0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; - - i2c4mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; - }; - i2c4mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - }; -}; + pca_cable_card_c04: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; -&i2c5 { - status = "okay"; + gpio-controller; + #gpio-cells = <2>; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; + led@0 { + label = "cablecard-c04-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; - i2c5mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; + led@1 { + label = "cablecard-c04-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; }; }; @@ -619,6 +870,62 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca_cable_card_c05: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c05-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c05-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c5mux0chn2: i2c@2 { @@ -629,6 +936,62 @@ compatible = "atmel,24c64"; reg = <0x52>; }; + + pca_cable_card_c06: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c06-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c06-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c5mux0chn3: i2c@3 { @@ -639,6 +1002,62 @@ compatible = "atmel,24c64"; reg = <0x53>; }; + + pca_cable_card_c07: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c07-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c07-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; }; }; @@ -659,8 +1078,64 @@ #size-cells = <0>; reg = <0>; eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c08: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c08-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c08-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; }; }; @@ -672,6 +1147,62 @@ compatible = "atmel,24c64"; reg = <0x52>; }; + + pca_cable_card_c09: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c09-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c09-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c6mux0chn2: i2c@2 { @@ -682,6 +1213,62 @@ compatible = "atmel,24c64"; reg = <0x53>; }; + + pca_cable_card_c10: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c10-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c10-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c6mux0chn3: i2c@3 { @@ -692,12 +1279,1013 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca_cable_card_c11: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c11-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c11-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; + }; + + pca_pcie_slot: pca9552@65 { + compatible = "nxp,pca9552"; + reg = <0x65>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + led@1 { + label = "pcieslot-c01"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "pcieslot-c02"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "pcieslot-c03"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "pcieslot-c04"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "pcieslot-c05"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "pcieslot-c06"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "pcieslot-c07"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "pcieslot-c08"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "pcieslot-c09"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "pcieslot-c10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "pcieslot-c11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; }; }; &i2c7 { status = "okay"; + + pic0_dimm: pca9552@31 { + compatible = "ibm,pca9552"; + reg = <0x31>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic1_dimm: pca9552@32 { + compatible = "ibm,pca9552"; + reg = <0x32>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm16"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm17"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm18"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm19"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm20"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm21"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm22"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm23"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm24"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm25"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm26"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm27"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm28"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm29"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm30"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm31"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic2_dimm: pca9552@33 { + compatible = "ibm,pca9552"; + reg = <0x33>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm32"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm33"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm34"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm35"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm36"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm37"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm38"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm39"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm40"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm41"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm42"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm43"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm44"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm45"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm46"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm47"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic3_dimm: pca9552@30 { + compatible = "ibm,pca9552"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm48"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm49"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm50"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm51"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm52"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm53"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm54"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm55"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm56"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm57"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm58"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm59"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm60"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm61"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm62"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm63"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic0_vrm_misc: pca9552@34 { + compatible = "ibm,pca9552"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "planar"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "tpm"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "cpu3-c61"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "cpu0-c14"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "opencapi-connector3"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "opencapi-connector4"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "opencapi-connector5"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + led@8 { + label = "vrm4"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "vrm5"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "vrm6"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "vrm7"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "vrm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "vrm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "vrm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "vrm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic1_vrm_misc: pca9552@35 { + compatible = "ibm,pca9552"; + reg = <0x35>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "dasd-backplane"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "power-distribution"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "cpu1-c19"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "cpu2-c56"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "opencapi-connector0"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "opencapi-connector1"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "opencapi-connector2"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + led@8 { + label = "vrm0"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "vrm1"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "vrm2"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "vrm3"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "vrm8"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "vrm9"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "vrm10"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "vrm11"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; &i2c8 { @@ -863,6 +2451,48 @@ compatible = "atmel,24c32"; reg = <0x50>; }; + + pca_oppanel: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; i2c14mux0chn3: i2c@3 { @@ -901,6 +2531,138 @@ }; }; + pca_fan_nvme: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "nvme4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "nvme5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "nvme6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "nvme7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "nvme8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "nvme9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "fan0"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "fan1"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "fan2"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "fan3"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + pca0: pca9552@61 { compatible = "nxp,pca9552"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts index f7fd3b3c90d0..342546a3c0f5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts @@ -19,33 +19,3 @@ reg = <0x6b>; }; }; - -&fan0 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan1 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan2 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan3 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan4 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan5 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 07593897fc9a..1752f3250e44 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts index 80c92e065a10..5a98a19f445e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory { diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 6e9baf3bba53..d5b7d28cda88 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts index c29e5f4d86ad..8f543cca7c21 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts index 084c455ad4cb..bcc1820f5c07 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts index 73319917cb74..3ef8358ff764 100644 --- a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index 42b37a204241..c0847636f20b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index 15c1f0ac81dc..a52a289cee85 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -57,7 +57,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts index 8503152faaf0..7d38d121ec6d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts index 91dced7e7849..3d4bdad27c2d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index eb4e93a57ff4..cd660c1ff3f5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index fd2e014dae75..084f54866f38 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -9,7 +9,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index d56b5ed09b37..4816486c0c9e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index c1478d2db602..e863ec088970 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -13,7 +13,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; + bootargs = "console=ttyS4,115200n8 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 01074b6e3e03..328ef472c479 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 85d58a63ae90..230f3584bcab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 4bcc82046362..7ae4ea0d2931 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -17,7 +17,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 03c161493ffc..61bc74b423cf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -14,7 +14,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index a68ff0675c28..9605e53f5bbf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -28,7 +28,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts index bc16ad2b5c80..50f3c6a5c0c8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts +++ b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d733c1f161c1..329eaeef66fb 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -264,6 +264,7 @@ reg-io-width = <4>; clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; resets = <&syscon ASPEED_RESET_CRT1>; + syscon = <&syscon>; status = "disabled"; interrupts = <0x19>; }; diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 7028e21bdd98..7e90d713f5e5 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -862,11 +862,21 @@ groups = "SGPM1"; }; + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; + pinctrl_sgps1_default: sgps1_default { function = "SGPS1"; groups = "SGPS1"; }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + pinctrl_sioonctrl_default: sioonctrl_default { function = "SIOONCTRL"; groups = "SIOONCTRL"; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 0025c88f660c..8ecb7861ce10 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -460,7 +460,7 @@ status = "disabled"; }; - nand: nand@18046000 { + nand_controller: nand-controller@18046000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>; diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index e8df458aad39..84cda16f68a2 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -179,7 +179,7 @@ status = "disabled"; }; - nand: nand@26000 { + nand_controller: nand-controller@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x26000 0x600>, <0x11b408 0x600>, diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index b4d2cc70afb1..748df7955ae6 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -269,7 +269,7 @@ dma-coherent; }; - nand: nand@26000 { + nand_controller: nand-controller@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, <0x11b408 0x600>, diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 3b4ab947492a..f24bdd0870a5 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -1,11 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2711.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2711-rpi.dtsi" #include "bcm283x-rpi-usb-peripheral.dtsi" -#include <dt-bindings/reset/raspberrypi,firmware-reset.h> - / { compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; model = "Raspberry Pi 4 Model B"; @@ -15,25 +13,12 @@ stdout-path = "serial1:115200n8"; }; - /* Will be filled by the bootloader */ - memory@0 { - device_type = "memory"; - reg = <0 0 0>; - }; - - aliases { - emmc2bus = &emmc2bus; - ethernet0 = &genet; - pcie0 = &pcie0; - blconfig = &blconfig; - }; - leds { - act { + led-act { gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; @@ -79,31 +64,15 @@ status = "okay"; }; -&firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; - - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_OFF", - "GLOBAL_RESET", - "VDD_SD_IO_SEL", - "CAM_GPIO", - "SD_PWR_ON", - ""; - status = "okay"; - }; - - reset: reset { - compatible = "raspberrypi,firmware-reset"; - #reset-cells = <1>; - }; +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + ""; }; &gpio { @@ -180,23 +149,13 @@ }; &hdmi0 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; status = "okay"; }; &hdmi1 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; status = "okay"; }; -&hvs { - clocks = <&firmware_clocks 4>; -}; - &pixelvalve0 { status = "okay"; }; @@ -219,22 +178,6 @@ status = "okay"; }; -&rmem { - /* - * RPi4's co-processor will copy the board's bootloader configuration - * into memory for the OS to consume. It'll also update this node with - * its placement information. - */ - blconfig: nvram@0 { - compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x0>; - no-map; - status = "disabled"; - }; -}; - /* SDHCI is used to control the SDIO for wireless */ &sdhci { #address-cells = <1>; @@ -309,10 +252,6 @@ status = "okay"; }; -&vchiq { - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; -}; - &vc4 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts new file mode 100644 index 000000000000..f4d2fc20397c --- /dev/null +++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711-rpi-4-b.dts" + +/ { + compatible = "raspberrypi,400", "brcm,bcm2711"; + model = "Raspberry Pi 400"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + /delete-node/ led-act; + + led-pwr { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + "SD_OC_N"; +}; + +&genet_mdio { + clock-frequency = <1950000>; +}; + +&pm { + /delete-property/ system-power-controller; +}; diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi new file mode 100644 index 000000000000..ca266c5d9f9b --- /dev/null +++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +#include <dt-bindings/reset/raspberrypi,firmware-reset.h> + +/ { + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0>; + }; + + aliases { + emmc2bus = &emmc2bus; + ethernet0 = &genet; + pcie0 = &pcie0; + blconfig = &blconfig; + }; +}; + +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; +}; + +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&rmem { + /* + * RPi4's co-processor will copy the board's bootloader configuration + * into memory for the OS to consume. It'll also update this node with + * its placement information. + */ + blconfig: nvram@0 { + compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; +}; + +&vchiq { + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 720beec54d61..b8a4096192aa 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -413,7 +413,7 @@ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; - emmc2: emmc2@7e340000 { + emmc2: mmc@7e340000 { compatible = "brcm,bcm2711-emmc2"; reg = <0x0 0x7e340000 0x100>; interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; @@ -1087,5 +1087,6 @@ }; &vec { + compatible = "brcm,bcm2711-vec"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 6c8ce39833bf..40b9405f1a8e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -14,11 +14,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 17fdd48346ff..11edb581dbaf 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -14,7 +14,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index b0355c229cdc..1b435c64bd9c 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -15,11 +15,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 33b3b5c02521..a23c25c00eea 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -15,7 +15,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 2b69957e0113..1b63d6b19750 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -15,7 +15,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi index 58059c2ce129..e4e6b6abbfc1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi @@ -5,7 +5,7 @@ / { leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index f65448c01e31..33b2b77aa47d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -23,7 +23,7 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 6dd93c6f4966..6f9b3a908f28 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -18,7 +18,7 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index d94357b21f7e..87ddcad76083 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -4,7 +4,7 @@ leds { compatible = "gpio-leds"; - act { + led-act { label = "ACT"; default-state = "keep"; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 0455a680394a..d8af8eeac7b6 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -15,11 +15,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index 28be0332c1c8..77099a7871b0 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -19,11 +19,11 @@ }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 37343148643d..61010266ca9a 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -20,11 +20,11 @@ }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 054ecaa355c9..dd4a48604097 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -20,7 +20,7 @@ }; leds { - act { + led-act { gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 925cb37c22f0..828a20561b96 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -14,7 +14,7 @@ * Since there is no upstream GPIO driver yet, * remove the incomplete node. */ - /delete-node/ act; + /delete-node/ led-act; }; reg_3v3: fixed-regulator { diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi index 20322de2f8bf..e2fd9610e125 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "otg"; - g-rx-fifo-size = <558>; + g-rx-fifo-size = <256>; g-np-tx-fifo-size = <32>; /* * According to dwc2 the sum of all device EP diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi index 1409d1b559c1..0ff0e9e25327 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "peripheral"; - g-rx-fifo-size = <558>; + g-rx-fifo-size = <256>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <256 256 512 512 512 768 768>; }; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index b83a864e2e8b..0f3be55201a5 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -420,7 +420,7 @@ status = "disabled"; }; - sdhci: sdhci@7e300000 { + sdhci: mmc@7e300000 { compatible = "brcm,bcm2835-sdhci"; reg = <0x7e300000 0x100>; interrupts = <2 30>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 8636600385fd..c81944cd6d0b 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -24,8 +24,8 @@ reg = <0x00000000 0x08000000>; }; - nand: nand@18028000 { - nandcs@0 { + nand_controller: nand-controller@18028000 { + nand@0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index e635a15041dd..a6e2aeb28675 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -25,8 +25,8 @@ <0x88000000 0x08000000>; }; - nand: nand@18028000 { - nandcs@0 { + nand_controller: nand-controller@18028000 { + nand@0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 2a8f7312d1be..6282363313e1 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -11,7 +11,7 @@ &pinctrl { compatible = "brcm,bcm4709-pinmux"; - pinmux_mdio: mdio { + pinmux_mdio: mdio-pins { groups = "mdio_grp"; function = "mdio"; }; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index 925a7c9ce5b7..be9a00ff752d 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -6,8 +6,8 @@ */ / { - nand@18028000 { - nandcs: nandcs@0 { + nand-controller@18028000 { + nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 7db72a2f1020..f92089290ccd 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -458,18 +458,18 @@ function = "spi"; }; - pinmux_i2c: i2c { + pinmux_i2c: i2c-pins { groups = "i2c_grp"; function = "i2c"; }; - pinmux_pwm: pwm { + pinmux_pwm: pwm-pins { groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; function = "pwm"; }; - pinmux_uart1: uart1 { + pinmux_uart1: uart1-pins { groups = "uart1_grp"; function = "uart1"; }; @@ -501,7 +501,7 @@ reg = <0x18004000 0x14>; }; - nand: nand@18028000 { + nand_controller: nand-controller@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; reg-names = "nand", "iproc-idm", "iproc-ext"; @@ -520,27 +520,27 @@ <0x1811b408 0x004>, <0x180293a0 0x01c>; reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "spi_lr_fullness_reached", + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", "spi_lr_session_aborted", "spi_lr_impatient", "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; + "spi_lr_overread"; clocks = <&iprocmed>; clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; - spi_nor: spi-nor@0 { + spi_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index 9c0325cf9e22..cca49a2e2d62 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -203,7 +203,7 @@ status = "disabled"; }; - nand: nand@2000 { + nand_controller: nand-controller@2000 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts index 8313b7cad542..f92d2cf85972 100644 --- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts +++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts @@ -14,10 +14,10 @@ }; }; -&nand { +&nand_controller { status = "okay"; - nandcs@1 { + nand@1 { compatible = "brcm,nandcs"; reg = <1>; nand-ecc-step-size = <512>; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 58f67c9b830b..5ac2042515b8 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -148,7 +148,7 @@ reg-names = "aon-ctrl", "aon-sram"; }; - nand: nand@3e2800 { + nand_controller: nand-controller@3e2800 { status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index b2d323f4a5ab..a76c74b44bba 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -82,8 +82,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index 046c59fb4846..de40bd59a5fa 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -49,8 +49,8 @@ }; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts index b4a1392bd5a6..dda3e11b711f 100644 --- a/arch/arm/boot/dts/bcm958300k.dts +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -60,8 +60,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts index 3378683321d3..ea3c6b88b313 100644 --- a/arch/arm/boot/dts/bcm958305k.dts +++ b/arch/arm/boot/dts/bcm958305k.dts @@ -68,8 +68,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 5443fc079e6e..1f73885ec274 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index e1e3c26cef19..b6b9ca8b0972 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index f161ba2e7e5e..ecf426f6ad5d 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -90,8 +90,8 @@ }; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index 83cb877d63db..8ca18da981ad 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -78,8 +78,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 4e106ce1384a..9747378db531 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -78,8 +78,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index cda6cc281e18..0f92b773afb8 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -89,8 +89,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index ffbff0014c65..9e984ca0e6df 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -68,8 +68,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index 5b177274f182..df5c8ab90627 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -31,10 +31,10 @@ status = "okay"; }; -&nand { +&nand_controller { status = "okay"; - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-strength = <4>; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 3fd39c479a3c..5475dab8181d 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 7cf31b6e48b7..c3942b4e82ad 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -574,8 +574,7 @@ status = "disabled"; }; ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; @@ -584,8 +583,7 @@ status = "disabled"; }; ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; @@ -593,9 +591,8 @@ power-domains = <&psc1 17>; status = "disabled"; }; - ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap0: pwm@306000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; clocks = <&psc1 20>; @@ -603,9 +600,8 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap1: pwm@307000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; clocks = <&psc1 20>; @@ -613,9 +609,8 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap2: pwm@308000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; clocks = <&psc1 20>; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 3551a64963f8..a9e7274806f4 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -314,8 +314,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <70>; - dmas = <&edma 58 0 &edma 59 0>; - dma-names = "tx", "rx"; }; i2c2: i2c@4802a000 { @@ -325,8 +323,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <71>; - dmas = <&edma 60 0 &edma 61 0>; - dma-names = "tx", "rx"; }; intc: interrupt-controller@48200000 { @@ -351,7 +347,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <0 0 0>; }; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 38530dbb89a0..87deb6a76eff 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -319,7 +319,7 @@ }; pcf_lcd: gpio@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -330,7 +330,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -362,11 +362,11 @@ clock-frequency = <400000>; pcf_hdmi: gpio@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi index a25749a1c365..a5bdc6431d8d 100644 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -5,17 +5,17 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 149144cdff35..956a26d52a4c 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1159,7 +1159,7 @@ ranges = <0x0 0x20000 0x1000>; uart3: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1343,7 +1343,7 @@ }; }; - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x55000 0x4>, <0x55010 0x4>, @@ -1376,7 +1376,7 @@ }; }; - target-module@57000 { /* 0x48057000, ap 15 06.0 */ + gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x57000 0x4>, <0x57010 0x4>, @@ -1562,7 +1562,7 @@ ranges = <0x0 0x66000 0x1000>; uart5: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1594,7 +1594,7 @@ ranges = <0x0 0x68000 0x1000>; uart6: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1626,7 +1626,7 @@ ranges = <0x0 0x6a000 0x1000>; uart1: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1658,7 +1658,7 @@ ranges = <0x0 0x6c000 0x1000>; uart2: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1690,7 +1690,7 @@ ranges = <0x0 0x6e000 0x1000>; uart4: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2424,7 +2424,7 @@ ranges = <0x0 0x20000 0x1000>; uart7: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2454,7 +2454,7 @@ ranges = <0x0 0x22000 0x1000>; uart8: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2484,7 +2484,7 @@ ranges = <0x0 0x24000 0x1000>; uart9: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2561,7 +2561,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -2607,7 +2607,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -2653,7 +2653,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -4129,28 +4129,6 @@ }; }; - usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x140000 0x4>, - <0x140010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x140000 0x20000>; - }; - target-module@170000 { /* 0x48970000, ap 21 0a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x170010 0x4>; @@ -4530,7 +4508,7 @@ ranges = <0x0 0xb000 0x1000>; uart10: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 6d2cca6b4488..a64364443031 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -187,7 +187,7 @@ }; &pcf_hdmi { - p0 { + hdmi-i2c-disable-hog { /* * PM_OEn to High: Disable routing I2C3 to PM_I2C * With this PM_SEL(p3) should not matter diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/dra71x.dtsi index cad0e4a2bd8d..9c270d8f75d5 100644 --- a/arch/arm/boot/dts/dra71x.dtsi +++ b/arch/arm/boot/dts/dra71x.dtsi @@ -11,7 +11,3 @@ &rtctarget { status = "disabled"; }; - -&usb4_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index b65b2dd094d0..f12825268188 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -226,7 +226,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -256,7 +256,7 @@ clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; @@ -268,7 +268,7 @@ */ lines-initial-states = <0x0f2b>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index d403acc754b6..90617261373c 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -77,12 +77,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -90,7 +90,7 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; @@ -108,7 +108,3 @@ &pcie2_rc { compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; }; - -&usb4_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi index b1147a4b77f9..3256631510c5 100644 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -6,7 +6,7 @@ #include "dra7-ipu-dsp-common.dtsi" &mailbox6 { - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index e1850d6c841a..cfb39dde4930 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -49,49 +49,6 @@ reg = <0x41500000 0x100>; }; - target-module@48940000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x48940000 0x4>, - <0x48940010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48940000 0x20000>; - - omap_dwc3_4: omap_dwc3_4@0 { - compatible = "ti,dwc3"; - reg = <0 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - }; target-module@41501000 { compatible = "ti,sysc-omap2", "ti,sysc"; @@ -188,12 +145,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -201,12 +158,12 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -224,3 +181,52 @@ &pcie2_rc { compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; }; + +&l4_per3 { + segment@0 { + usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x140000 0x4>, + <0x140010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x140000 0x20000>; + + omap_dwc3_4: omap_dwc3_4@0 { + compatible = "ti,dwc3"; + reg = <0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 9bd01ae40b1d..e2b7fcb061cf 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -158,12 +158,6 @@ regulator-max-microvolt = <1800000>; }; - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; @@ -355,7 +349,7 @@ }; pcf_lcd: pcf8757@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -366,7 +360,7 @@ }; pcf_gpio_21: pcf8757@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; @@ -377,11 +371,11 @@ }; pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; @@ -406,27 +400,6 @@ }; }; -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - &cpu0 { vdd-supply = <&buck10_reg>; }; @@ -573,14 +546,6 @@ }; }; -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; - &ipu2 { status = "okay"; memory-region = <&ipu2_cma_pool>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index c52b9cf4f74c..f6ba5e426040 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -653,7 +653,7 @@ mmc-pwrseq = <&wlan_pwrseq>; brcmf: wifi@1 { - compatible = "brcm,bcm4334-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx1>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 525ff3d2fac3..55922176807e 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -314,7 +314,8 @@ }; &fimc_1 { - status = "okay"; + /* Back camera not implemented */ + status = "disabled"; assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; assigned-clock-parents = <&clock CLK_SCLK_MPLL>; @@ -330,7 +331,8 @@ }; &fimc_3 { - status = "okay"; + /* Back camera not implemented */ + status = "disabled"; assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; assigned-clock-parents = <&clock CLK_SCLK_MPLL>; @@ -806,7 +808,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index d2406c9146b8..3eb8df319246 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -521,7 +521,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index dd44ad2c6ad6..f052853244a4 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -614,7 +614,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 4583d342af39..b3726d4d7d93 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -163,6 +163,7 @@ <1025000>, <950000>, <918750>, <900000>, <875000>, <831250>; + wakeup-source; regulators { ldo1_reg: LDO1 { diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index fc77c1bfd844..968c7943653e 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -668,6 +668,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&max77686_irq>; pinctrl-names = "default"; + wakeup-source; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index c49dbb7847b8..2c792142605c 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -50,8 +50,8 @@ reg = <0x48>; interrupt-parent = <&gpm2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; avdd-supply = <&ldo23_reg>; vdd-supply = <&ldo24_reg>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 5bd05866d7a3..5b1d4591b35c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -282,6 +282,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; + wakeup-source; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e1f6de53e20e..5479ef09f9f3 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -144,6 +144,7 @@ <1200000>, <1200000>, <1200000>, <1200000>, <1200000>, <1200000>; + wakeup-source; s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 9e750890edb8..22c3086e0076 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -325,6 +325,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&max77686_irq>; pinctrl-names = "default"; + wakeup-source; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index a161f6237c7f..a771542e28b8 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -218,6 +218,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s5m8767_irq>; + wakeup-source; vinb1-supply = <&main_dc_reg>; vinb2-supply = <&main_dc_reg>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 949c0721cdb4..884fef55836c 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -190,6 +190,7 @@ pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; #clock-cells = <1>; inl1-supply = <&buck5_reg>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 1aad4859c5f1..dfc7f14f5772 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -352,6 +352,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s2mps11_irq>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index d506da9fa661..a4f0e3ffedbd 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -132,6 +132,7 @@ pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 6d690b1db099..e7958dbecfd2 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -512,6 +512,7 @@ interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s2mps11_irq>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 20c222b33f98..d91f7fa2cf80 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -22,7 +22,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index ede782257643..1c24f9b35973 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -24,7 +24,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 2fc3e86dc5f7..982752e1df24 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -22,7 +22,7 @@ * Green LED is much brighter than the others * so limit its max brightness */ - max_brightness = <127>; + max-brightness = <127>; linux,default-trigger = "mmc0"; }; @@ -30,7 +30,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index cc39289e99dd..c79a2a02dd6b 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -61,9 +61,9 @@ #size-cells = <0>; /* Collides with IDE pins, that's cool (we do not use them) */ - gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; num-chipselects = <1>; @@ -169,7 +169,7 @@ * The touchpad input is connected to a GPIO bit-banged * I2C bus. */ - gpio-i2c { + i2c { compatible = "i2c-gpio"; /* Collides with ICE */ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -492,8 +492,7 @@ display-controller@6a000000 { status = "okay"; - port@0 { - reg = <0>; + port { display_out: endpoint { remote-endpoint = <&panel_in>; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index c6f3d90e3e90..eba1c94ed7f7 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -82,7 +82,7 @@ /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ - gpio-i2c { + i2c { compatible = "i2c-gpio"; sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -140,7 +140,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; /* Uses MDC and MDIO */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 43c45f7e1e0a..13112a8a5dd8 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -62,7 +62,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index 9611ddf06792..0ebda4efd9d0 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -56,7 +56,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ @@ -125,18 +125,6 @@ }; }; - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - usb@68000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts index a0916d3c1059..c78e55fd2562 100644 --- a/arch/arm/boot/dts/gemini-sl93512r.dts +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -87,9 +87,9 @@ #address-cells = <1>; #size-cells = <0>; /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 0c6e6d35bfaa..1b64cc80b55a 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -72,9 +72,9 @@ #address-cells = <1>; #size-cells = <0>; /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index 3a2761dd460f..5602ba8f30f2 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -68,7 +68,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index 52b4dbc0c072..a4a260c36d75 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -67,7 +67,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 065ed10a79fa..cc053af3c347 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -191,7 +191,7 @@ }; rtc@45000000 { - compatible = "cortina,gemini-rtc"; + compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; reg = <0x45000000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_RTC>; @@ -286,6 +286,7 @@ clock-names = "PCLK", "PCICLK"; pinctrl-names = "default"; pinctrl-0 = <&pci_default_pins>; + device_type = "pci"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; @@ -356,6 +357,14 @@ }; }; + crypto: crypto@62000000 { + compatible = "cortina,sl3516-crypto"; + reg = <0x62000000 0x10000>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_SECURITY>; + clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; + }; + ide@63000000 { compatible = "cortina,gemini-pata", "faraday,ftide010"; reg = <0x63000000 0x1000>; @@ -409,8 +418,6 @@ clock-names = "PCLK", "TVE"; pinctrl-names = "default"; pinctrl-0 = <&tvc_default_pins>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 905900bf3e82..cf48ec14af43 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. Hi3620 SoC + * HiSilicon Ltd. Hi3620 SoC * - * Copyright (C) 2012-2013 Hisilicon Ltd. + * Copyright (C) 2012-2013 HiSilicon Ltd. * Copyright (C) 2012-2013 Linaro Ltd. * * Author: Haojian Zhuang <haojian.zhuang@linaro.org> diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts index 031476304d94..f3faf247cd61 100644 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP01 SoC + * HiSilicon Ltd. HiP01 SoC * - * Copyright (C) 2014 Hisilicon Ltd. + * Copyright (C) 2014 HiSilicon Ltd. * Copyright (C) 2014 Huawei Ltd. * * Author: Wang Long <long.wanglong@huawei.com> diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 2a7963605390..e17f36bd9006 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP01 SoC + * HiSilicon Ltd. HiP01 SoC * - * Copyright (c) 2014 Hisilicon Ltd. + * Copyright (c) 2014 HiSilicon Ltd. * Copyright (c) 2014 Huawei Ltd. * * Author: Wang Long <long.wanglong@huawei.com> diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index bccf5ba3d855..2424cc545c9c 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP04 SoC + * HiSilicon Ltd. HiP04 SoC * - * Copyright (C) 2013-2014 Hisilicon Ltd. + * Copyright (C) 2013-2014 HiSilicon Ltd. * Copyright (C) 2013-2014 Linaro Ltd. * * Author: Haojian Zhuang <haojian.zhuang@linaro.org> diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 22b122d3f514..7758c19038f0 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 HiSilicon Limited. */ /dts-v1/; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 97211385dc89..dc991ba2a9fb 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 HiSilicon Limited. */ #include <dt-bindings/clock/hix5hd2-clock.h> diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index f984b702efc5..908caf810351 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -563,15 +563,15 @@ #define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 #define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 -#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000 +#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000 #define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 #define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 -#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000 +#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000 #define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 #define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 -#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000 +#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000 #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 @@ -580,18 +580,18 @@ #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 #define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 -#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 +#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000 #define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 #define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 -#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 +#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 #define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 #define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 -#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000 +#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000 #define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 #define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/imx28-lwe.dtsi new file mode 100644 index 000000000000..bb971e660db8 --- /dev/null +++ b/arch/arm/boot/dts/imx28-lwe.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + aliases { + spi2 = &ssp3; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1"; + }; + + memory@40000000 { + reg = <0x40000000 0x08000000>; + }; + + reg_3v3: regulator-reg-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_5v: regulator-reg-usb-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_fec_3v3: regulator-reg-fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&spi3_pins_a { + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + MX28_PAD_AUART2_TX__GPIO_3_9 + >; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_3v3>; + non-removable; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&ssp3 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_a>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x80000>; + read-only; + }; + + partition@80000 { + label = "env0"; + reg = <0x80000 0x10000>; + }; + + partition@90000 { + label = "env1"; + reg = <0x90000 0x10000>; + }; + + partition@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "swupdate"; + reg = <0x500000 0x800000>; + }; + }; + }; +}; + +&usb0 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_b>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/imx28-xea.dts new file mode 100644 index 000000000000..a400c108f66a --- /dev/null +++ b/arch/arm/boot/dts/imx28-xea.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + compatible = "lwn,imx28-xea", "fsl,imx28"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a &hog_pins_tiva>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D02__GPIO_0_2 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_CLE__GPIO_0_27 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_LCD_D00__GPIO_1_0 + MX28_PAD_LCD_D01__GPIO_1_1 + MX28_PAD_LCD_D02__GPIO_1_2 + MX28_PAD_LCD_D03__GPIO_1_3 + MX28_PAD_LCD_D04__GPIO_1_4 + MX28_PAD_LCD_D05__GPIO_1_5 + MX28_PAD_LCD_D06__GPIO_1_6 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + hog_pins_tiva: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_WRN__GPIO_0_25 + >; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + hog_pins_coding: hog@2 { + reg = <2>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D01__GPIO_0_1 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; +}; + +®_fec_3v3 { + gpio = <&gpio0 0 0>; +}; + +®_usb_5v { + gpio = <&gpio0 2 0>; +}; + +&spi2_pins_a { + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__GPIO_2_19 + >; +}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 16addb3a2a1b..7d4970417dce 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -206,7 +206,7 @@ pinctrl-0 = <&pinctrl_weim>; status = "okay"; - lan9221: lan9221@5,0 { + lan9221: ethernet@5,0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lan9221>; compatible = "smsc,lan9221", "smsc,lan9115"; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 9a2e1fde7128..6208fbb2e741 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -24,7 +24,7 @@ reg = <0xf4000000 0x3ff0000>; ranges; - lan9220@f4000000 { + ethernet@f4000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0xf4000000 0x2000000>; phy-mode = "mii"; diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts new file mode 100644 index 000000000000..411aa72d344b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b105pv2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B105Pv2"; + compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts new file mode 100644 index 000000000000..d011127c635b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b105v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B105v2"; + compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts new file mode 100644 index 000000000000..ca840fa84052 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b125pv2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B125Pv2"; + compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts new file mode 100644 index 000000000000..81e5a9cb8900 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b125v2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B125v2"; + compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts new file mode 100644 index 000000000000..c861937b30f6 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b155v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B155v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B155v2"; + compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g156xtn01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h84"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi new file mode 100644 index 000000000000..ec5b66453156 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5Pv2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include <dt-bindings/input/input.h> +#include "imx6dl-qmx6.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + /* Do not allow frequencies above 800MHz */ + cpus { + cpu@0 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + + cpu@1 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + }; + + reg_syspwr: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "SYS_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_5v_pmc: regulator-5v-pmc { + compatible = "regulator-fixed"; + regulator-name = "5V PMC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_syspwr>; + }; + + reg_5v0_audio: regulator-5v0-audio { + compatible = "regulator-fixed"; + regulator-name = "5V0_AUDIO"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This must be always-on for da7212, which has some not + * properly documented dependencies for it's speaker supply + * pin. The issue manifests as speaker volume being very low. + */ + regulator-always-on; + }; + + + reg_3v3_audio: regulator-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-0 = <&pinctrl_q7_hda_reset>; + pinctrl-names = "default"; + gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5_audio: regulator-2v5-audio { + compatible = "regulator-fixed"; + regulator-name = "2V5_AUDIO"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <®_3v3_audio>; + + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "WLAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sdio_power>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; + + reg_bl: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "LED_VCC"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_syspwr>; + pinctrl-0 = <&pinctrl_q7_lcd_power>; + pinctrl-names = "default"; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + usb_power: regulator-usb-power { + compatible = "regulator-fixed"; + regulator-name = "USB POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + charger: battery-charger { + compatible = "gpio-charger"; /* ti,bq24172 */ + charger-type = "mains"; + gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>; + charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>, + <&tca6424a 12 GPIO_ACTIVE_HIGH>; + charge-current-limit-mapping = <1300000 0x0>, + <700000 0x1>, + <0 0x2>; + charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>; + }; + + poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_spi_cs1>; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; + + power-button-key { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sleep_button>; + + power-button { + label = "power button"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + }; + }; + + rotary-encoder-key { + compatible = "gpio-keys"; + + rotary-encoder-press { + label = "rotary-encoder press"; + gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + linux,can-disable; + }; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>; + rotary-encoder,relative-axis; + rotary-encoder,steps-per-period = <2>; + wakeup-source; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; + + alarm1 { + label = "alarm:red"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + alarm2 { + label = "alarm:yellow"; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + }; + + alarm3 { + label = "alarm:blue"; + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_backlight_enable>; + power-supply = <®_bl>; + pwms = <&pwm4 0 5000000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <179>; + enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + panel { + backlight = <&backlight>; + power-supply = <®_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = "Speaker", "Ext Spk"; + simple-audio-card,audio-routing = "Ext Spk", "LINE"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + battery: battery@b { + compatible = "ti,bq20z65", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>; + sbs,i2c-retry-count = <5>; + power-supplies = <&charger>; + }; + + codec: audio-codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5_audio>; + VDDSP-supply = <®_5v0_audio>; + VDDMIC-supply = <®_3v3_audio>; + VDDIO-supply = <®_3v3_audio>; + clocks = <&clk_ext_audio_codec>; + clock-names = "mclk"; + }; +}; + +&i2c5 { + tca6424a: gpio-controller@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN", + "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF", + "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0", + "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "", + "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", + "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2"; + + }; + + tmp75: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + vs-supply = <®_3v3>; + interrupt-parent = <&tca6424a>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&usb_power>; + disable-over-current; + dr_mode = "host"; + status = "okay"; + + /* + * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N. + * On QMX6 this is not connceted to the i.MX6, but to the USB Hub + * from &usbh1. This means, that we cannot easily detect and handle + * over-current events. Fortunately the regulator limits the current + * automatically, so the hardware is still protected. + */ +}; + +&usdhc4 { + /* WiFi module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + vmmc-supply = <®_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio7>; + + interrupt-parent = <&gpio4>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi new file mode 100644 index 000000000000..a326a331508e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5v2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include <dt-bindings/input/input.h> +#include "imx6dl-b1x5pv2.dtsi" + +/ { + reg_3v3_acm: regulator-3v3-acm { + compatible = "regulator-fixed"; + regulator-name = "3V3 ACM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_3v3>; + }; +}; + +&i2c1 { + tca6416: gpio-controller@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3v3_acm>; + gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2", + "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1", + "ACM2_CL2", "", "", "", + "", "", "", ""; + + /* + * The interrupt pin is connected to &tca6424a pin 1, but the Linux + * TCA6424 driver cannot handle low type interrupts at the moment + * (and support cannot be added without some ugly hacks). Since this + * controller does not have any input type GPIOs, just pretend + * that the interrupt pin is unconnected. + */ + }; +}; + +&i2c5 { + mpl3115a2: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + vcc-supply = <®_3v3_acm>; + + /* + * The MPL3115 interrupts are connected to pin 22 and 23 + * of &tca6424a, but the binding does not yet support + * interrupts. + */ + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 4d0d3d3386af..60fe5f14666e 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -138,8 +138,6 @@ interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; touchscreen-max-pressure = <4095>; @@ -147,7 +145,9 @@ ti,vref-delay-usecs = /bits/ 16 <100>; ti,x-plate-ohms = /bits/ 16 <800>; ti,y-plate-ohms = /bits/ 16 <300>; - + ti,debounce-max = /bits/ 16 <3>; + ti,debounce-tol = /bits/ 16 <70>; + ti,debounce-rep = /bits/ 16 <3>; wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index ae6da241f13e..190d26642bc8 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -21,14 +21,11 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 500000>; + pwms = <&pwm1 0 500000 0>; brightness-levels = <0 20 81 248 1000>; default-brightness-level = <20>; num-interpolated-steps = <21>; power-supply = <®_bl_12v0>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; keys { @@ -223,6 +220,24 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; + + touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-0 = <&pinctrl_tsc>; + pinctrl-names ="default"; + spi-max-frequency = <100000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + touchscreen-max-pressure = <4095>; + ti,vref-delay-usecs = /bits/ 16 <100>; + ti,x-plate-ohms = /bits/ 16 <800>; + ti,y-plate-ohms = /bits/ 16 <300>; + ti,debounce-max = /bits/ 16 <3>; + ti,debounce-tol = /bits/ 16 <70>; + ti,debounce-rep = /bits/ 16 <3>; + wakeup-source; + }; }; &i2c1 { @@ -261,7 +276,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -276,8 +290,6 @@ }; &ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; status = "okay"; }; @@ -285,10 +297,6 @@ status = "disabled"; }; -&vpu { - status = "disabled"; -}; - &iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < @@ -300,12 +308,6 @@ >; }; - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - pinctrl_can1phy: can1phy { fsl,pins = < /* CAN1_SR */ diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi new file mode 100644 index 000000000000..150d69858255 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for i.MX6DL based congatec QMX6 +// System on Module +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora +// Copyright 2016 congatec AG + +#include "imx6dl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c2>; + + i2c5: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) + >; + }; + + audmux_aud6 { + fsl,audmux-port = <MX51_AUDMUX_PORT6>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&clks { + clocks = <&rtc_sqw>; + clock-names = "ckil"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf032b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "bootloader"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "user"; + reg = <0x0100000 0x2fc000>; + }; + + partition@3fc000 { + label = "reserved"; + reg = <0x03fc000 0x4000>; + read-only; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@6 { + reg = <6>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + rtc: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + + rtc_sqw: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&i2c6 { + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt |