diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2016-02-23 12:04:58 +0000 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2016-03-07 09:23:38 +0000 |
| commit | 4e85e4fd11cab1b16b5ad1037fbdbd56a85d7d21 (patch) | |
| tree | 883294ceae99d77c4b839f0880035f96a95a0b81 | |
| parent | 9931932bfd3429aa8e98c33a26dfafcdbda71a43 (diff) | |
Initialize secondary CPUs during cold boot
The previous reset code in BL1 performed the following steps in
order:
1. Warm/Cold boot detection.
If it's a warm boot, jump to warm boot entrypoint.
2. Primary/Secondary CPU detection.
If it's a secondary CPU, jump to plat_secondary_cold_boot_setup(),
which doesn't return.
3. CPU initialisations (cache, TLB...).
4. Memory and C runtime initialization.
For a secondary CPU, steps 3 and 4 are never reached. This shouldn't
be a problem in most cases, since current implementations of
plat_secondary_cold_boot_setup() either panic or power down the
secondary CPUs.
The main concern is the lack of secondary CPU initialization when
bare metal EL3 payloads are used in case they don't take care of this
initialisation themselves.
This patch moves the detection of primary/secondary CPU after step 3
so that the CPU initialisations are performed per-CPU, while the
memory and the C runtime initialisation are only performed on the
primary CPU. The diagrams used in the ARM Trusted Firmware Reset
Design documentation file have been updated to reflect the new boot
flow.
Platforms ports might be affected by this patch depending on the
behaviour of plat_secondary_cold_boot_setup(), as the state of the
platform when entering this function will be different.
Fixes ARM-software/tf-issues#342
Change-Id: Icbf4a0ee2a3e5b856030064472f9fa6696f2eb9e
| -rw-r--r-- | docs/diagrams/default_reset_code.png | bin | 60028 -> 41796 bytes | |||
| -rw-r--r-- | docs/diagrams/reset_code_flow.dia | bin | 4318 -> 4399 bytes | |||
| -rw-r--r-- | docs/diagrams/reset_code_no_boot_type_check.png | bin | 59028 -> 42942 bytes | |||
| -rw-r--r-- | docs/diagrams/reset_code_no_checks.png | bin | 51209 -> 39753 bytes | |||
| -rw-r--r-- | docs/diagrams/reset_code_no_cpu_check.png | bin | 52471 -> 38566 bytes | |||
| -rw-r--r-- | include/common/el3_common_macros.S | 21 |
6 files changed, 14 insertions, 7 deletions
diff --git a/docs/diagrams/default_reset_code.png b/docs/diagrams/default_reset_code.png Binary files differindex e7e0d855..d8675e4a 100644 --- a/docs/diagrams/default_reset_code.png +++ b/docs/diagrams/default_reset_code.png diff --git a/docs/diagrams/reset_code_flow.dia b/docs/diagrams/reset_code_flow.dia Binary files differindex 5de00dad..133c9cf6 100644 --- a/docs/diagrams/reset_code_flow.dia +++ b/docs/diagrams/reset_code_flow.dia diff --git a/docs/diagrams/reset_code_no_boot_type_check.png b/docs/diagrams/reset_code_no_boot_type_check.png Binary files differindex 8ce7e97a..23e865f6 100644 --- a/docs/diagrams/reset_code_no_boot_type_check.png +++ b/docs/diagrams/reset_code_no_boot_type_check.png diff --git a/docs/diagrams/reset_code_no_checks.png b/docs/diagrams/reset_code_no_checks.png Binary files differindex 8a02f0f8..26a179bc 100644 --- a/docs/diagrams/reset_code_no_checks.png +++ b/docs/diagrams/reset_code_no_checks.png diff --git a/docs/diagrams/reset_code_no_cpu_check.png b/docs/diagrams/reset_code_no_cpu_check.png Binary files differindex 8b05ea4d..4150dbef 100644 --- a/docs/diagrams/reset_code_no_cpu_check.png +++ b/docs/diagrams/reset_code_no_cpu_check.png diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S index 6f7136f9..32df7d76 100644 --- a/include/common/el3_common_macros.S +++ b/include/common/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -171,9 +171,19 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + .if \_secondary_cold_boot /* ------------------------------------------------------------- - * It is a cold boot. + * Check if this is a primary or secondary CPU cold boot. * The primary CPU will set up the platform while the * secondaries are placed in a platform-specific state until the * primary CPU performs the necessary actions to bring them out @@ -193,13 +203,10 @@ .endif /* _secondary_cold_boot */ /* --------------------------------------------------------------------- - * Perform any processor specific actions upon reset e.g. cache, TLB - * invalidations etc. + * Initialize memory now. Secondary CPU initialization won't get to this + * point. * --------------------------------------------------------------------- */ - bl reset_handler - - el3_arch_init_common \_exception_vectors .if \_init_memory bl platform_mem_init |
