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authorCaesar Wang <wxt@rock-chips.com>2016-08-09 08:15:44 +0800
committerCaesar Wang <wxt@rock-chips.com>2016-08-11 13:12:10 +0800
commit545bff0e1e43f9ec6303fb93f4ba992d1ba1dd70 (patch)
treea3aa0e8fae7651f45b0e91df1b021d3418d91737
parent5d3b10675320aadbb1855a836d65bcd633581f7c (diff)
rockchip: fix the power up/dowm cnt for rk3399
Sometimes this will cause the long delay for suspend/resume. Since the 24M OCS will be turned off in power mode. Also, remove the ERROR_DEPRECATED config define. Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a
-rw-r--r--plat/rockchip/common/pmusram/pmu_sram_cpus_on.S2
-rw-r--r--plat/rockchip/rk3399/drivers/pmu/pmu.c39
2 files changed, 34 insertions, 7 deletions
diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 3378272c..9f94b0c1 100644
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -70,9 +70,7 @@ sys_resume:
psram_data:
.quad PSRAM_DT_BASE
sys_wakeup_entry:
-#if !ERROR_DEPRECATED
.quad psci_entrypoint
-#endif
pmu_cpuson_entrypoint_end:
.word 0
endfunc pmu_cpuson_entrypoint
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 507cb72e..00596774 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -777,6 +777,36 @@ static void sys_slp_config(void)
mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN));
mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
+ /*
+ * About to switch PMU counters to 32K; switch all timings to 32K
+ * for simplicity even if we don't plan on using them.
+ */
+ mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(3));
+
+ mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG));
+
+ mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
+ mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K);
+ mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */
+}
+
+static void sys_slp_unconfig(void)
+{
+ /*
+ * About to switch PMU counters to 24M; switch all timings to 24M
+ * for simplicity even if we don't plan on using them.
+ */
mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_MS(3));
@@ -784,16 +814,13 @@ static void sys_slp_config(void)
mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_24M_CNT_MS(3));
- mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(3));
+ mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_MS(3));
mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(3));
- mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG));
- mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
- mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K);
- mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /*32k iomux*/
+ mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG));
}
static void set_hw_idle(uint32_t hw_idle)
@@ -874,6 +901,8 @@ static int sys_pwr_domain_resume(void)
pmu_sgrf_rst_hld();
+ sys_slp_unconfig();
+
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);