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| author | danh-arm <dan.handley@arm.com> | 2016-08-17 12:54:38 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-08-17 12:54:38 +0100 |
| commit | 6700ae65fb8c281e92bc58ca5396a1a39c812762 (patch) | |
| tree | ad9f3908b2f118ae6b764ce8fa693f7e7e45e7be | |
| parent | d3ca949f00623e75c0d0a45c3264d9b388262df5 (diff) | |
| parent | 65d68ca64d12a4ce5b05a96808dd6f638451940d (diff) | |
Merge pull request #682 from sudeep-holla/gicv3_ns_intr
gicv3: disable Group1 NonSecure interrupts during core powerdown
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 6c6c7af9..e0170338 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -280,9 +280,10 @@ void gicv3_cpuif_disable(unsigned int proc_num) write_icc_igrpen0_el1(read_icc_igrpen0_el1() & ~IGRPEN1_EL1_ENABLE_G0_BIT); - /* Disable Group1 Secure interrupts */ + /* Disable Group1 Secure and Non-Secure interrupts */ write_icc_igrpen1_el3(read_icc_igrpen1_el3() & - ~IGRPEN1_EL3_ENABLE_G1S_BIT); + ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | + IGRPEN1_EL3_ENABLE_G1S_BIT)); /* Synchronise accesses to group enable registers */ isb(); |