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authorJuan Castillo <juan.castillo@arm.com>2014-04-28 12:48:40 +0100
committerJuan Castillo <juan.castillo@arm.com>2014-05-13 11:51:08 +0100
commit42a52d89e78a0df5be1f64a3b2e394289413e498 (patch)
tree544dc831dfebd8035f110491703ecdadd079a8e5 /common/debug.c
parent60bc4bbd0bf705f30327e3c37973bcf1e1851110 (diff)
Fix C accessors to GIC distributor registers with set/clear semantics
This patch fixes C accessors to GIC registers that follow a set/clear semantic to change the state of an interrupt, instead of read/write/modify. These registers are: Set-Enable Clear-Enable Set-Pending Clear-Pending Set-Active Clear-Active For instance, to enable an interrupt we write a one to the corresponding bit in the Set-Enable register, whereas to disable it we write a one to the corresponding bit in the Clear-Enable register. Fixes ARM-software/tf-issues#137 Change-Id: I3b66bad94d0b28e0fe08c9042bac0bf5ffa07944
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