diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2013-12-05 14:21:04 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-01-20 18:45:04 +0000 |
| commit | a59caa4cbd03c394e7a5bf098ddd9db457b35aae (patch) | |
| tree | a6ee2402c1c446a352974b8ff68a67a611187344 /common/psci/psci_afflvl_suspend.c | |
| parent | 03cb8fbb5d769affd508c97a5327544e487eb1a9 (diff) | |
psci: replace secure context with suspend context
The secure context saved and restored across a cpu_suspend operation
can be more than just the state of the secure system registers e.g. we
also need to save the affinity level till which the cpu is being
powered down. This patch creates a suspend_context data structure
which includes the system register context. This will allow other bits
to be saved and restored as well in subsequent patches.
Change-Id: I1c1f7d25497388b54b7d6ee4fab77e8c6a9992c4
Diffstat (limited to 'common/psci/psci_afflvl_suspend.c')
| -rw-r--r-- | common/psci/psci_afflvl_suspend.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/common/psci/psci_afflvl_suspend.c b/common/psci/psci_afflvl_suspend.c index d91b9210..6fb60f4a 100644 --- a/common/psci/psci_afflvl_suspend.c +++ b/common/psci/psci_afflvl_suspend.c @@ -73,16 +73,16 @@ static int psci_afflvl0_suspend(unsigned long mpidr, * Arch. management: Save the secure context, flush the * L1 caches and exit intra-cluster coherency et al */ - psci_secure_context[index].sctlr = read_sctlr(); - psci_secure_context[index].scr = read_scr(); - psci_secure_context[index].cptr = read_cptr(); - psci_secure_context[index].cpacr = read_cpacr(); - psci_secure_context[index].cntfrq = read_cntfrq_el0(); - psci_secure_context[index].mair = read_mair(); - psci_secure_context[index].tcr = read_tcr(); - psci_secure_context[index].ttbr = read_ttbr0(); - psci_secure_context[index].vbar = read_vbar(); - psci_secure_context[index].pstate = + psci_suspend_context[index].sec_sysregs.sctlr = read_sctlr(); + psci_suspend_context[index].sec_sysregs.scr = read_scr(); + psci_suspend_context[index].sec_sysregs.cptr = read_cptr(); + psci_suspend_context[index].sec_sysregs.cpacr = read_cpacr(); + psci_suspend_context[index].sec_sysregs.cntfrq = read_cntfrq_el0(); + psci_suspend_context[index].sec_sysregs.mair = read_mair(); + psci_suspend_context[index].sec_sysregs.tcr = read_tcr(); + psci_suspend_context[index].sec_sysregs.ttbr = read_ttbr0(); + psci_suspend_context[index].sec_sysregs.vbar = read_vbar(); + psci_suspend_context[index].sec_sysregs.pstate = read_daif() & (DAIF_ABT_BIT | DAIF_DBG_BIT); /* Set the secure world (EL3) re-entry point after BL1 */ @@ -411,18 +411,18 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, * Arch. management: Restore the stashed secure architectural * context in the right order. */ - write_vbar(psci_secure_context[index].vbar); - write_daif(read_daif() | psci_secure_context[index].pstate); - write_mair(psci_secure_context[index].mair); - write_tcr(psci_secure_context[index].tcr); - write_ttbr0(psci_secure_context[index].ttbr); - write_sctlr(psci_secure_context[index].sctlr); + write_vbar(psci_suspend_context[index].sec_sysregs.vbar); + write_daif(read_daif() | psci_suspend_context[index].sec_sysregs.pstate); + write_mair(psci_suspend_context[index].sec_sysregs.mair); + write_tcr(psci_suspend_context[index].sec_sysregs.tcr); + write_ttbr0(psci_suspend_context[index].sec_sysregs.ttbr); + write_sctlr(psci_suspend_context[index].sec_sysregs.sctlr); /* MMU and coherency should be enabled by now */ - write_scr(psci_secure_context[index].scr); - write_cptr(psci_secure_context[index].cptr); - write_cpacr(psci_secure_context[index].cpacr); - write_cntfrq_el0(psci_secure_context[index].cntfrq); + write_scr(psci_suspend_context[index].sec_sysregs.scr); + write_cptr(psci_suspend_context[index].sec_sysregs.cptr); + write_cpacr(psci_suspend_context[index].sec_sysregs.cpacr); + write_cntfrq_el0(psci_suspend_context[index].sec_sysregs.cntfrq); /* * Generic management: Now we just need to retrieve the |