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| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2014-02-06 10:36:15 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-02-17 18:51:44 +0000 |
| commit | caa84939a4d8b1189dea8619ccc57bdb3026b125 (patch) | |
| tree | a7eb5e977cc9971c051ef469877fc3d00cba24ad /common/psci/psci_entry.S | |
| parent | 07f4e078b6871e5c74f6cb38f2726a2cfcb2b746 (diff) | |
Add support for handling runtime service requests
This patch uses the reworked exception handling support to handle
runtime service requests through SMCs following the SMC calling
convention. This is a giant commit since all the changes are
inter-related. It does the following:
1. Replace the old exception handling mechanism with the new one
2. Enforce that SP_EL0 is used C runtime stacks.
3. Ensures that the cold and warm boot paths use the 'cpu_context'
structure to program an ERET into the next lower EL.
4. Ensures that SP_EL3 always points to the next 'cpu_context'
structure prior to an ERET into the next lower EL
5. Introduces a PSCI SMC handler which completes the use of PSCI as a
runtime service
Change-Id: I661797f834c0803d2c674d20f504df1b04c2b852
Co-authored-by: Achin Gupta <achin.gupta@arm.com>
Diffstat (limited to 'common/psci/psci_entry.S')
| -rw-r--r-- | common/psci/psci_entry.S | 34 |
1 files changed, 15 insertions, 19 deletions
diff --git a/common/psci/psci_entry.S b/common/psci/psci_entry.S index 28a41436..15e074c3 100644 --- a/common/psci/psci_entry.S +++ b/common/psci/psci_entry.S @@ -34,6 +34,7 @@ #include <psci_private.h> #include <runtime_svc.h> #include <asm_macros.S> +#include <cm_macros.S> .globl psci_aff_on_finish_entry .globl psci_aff_suspend_finish_entry @@ -74,6 +75,13 @@ psci_aff_common_finish_entry: msr vbar_el3, x0 isb + /* --------------------------------------------- + * Use SP_EL0 for the C runtime stack. + * --------------------------------------------- + */ + msr spsel, #0 + isb + bl read_mpidr mov x19, x0 bl platform_set_coherent_stack @@ -102,31 +110,19 @@ psci_aff_common_finish_entry: bl platform_set_stack /* --------------------------------------------- - * Now that the execution stack has been set + * Now that the context management has been set * up, enable full runtime exception handling. - * Since we're just about to leave this EL with - * ERET, we don't need an ISB here + * SP_EL3 is pointing to a 'cpu_context' + * structure which has an exception stack + * allocated. Since we're just about to leave + * this EL with ERET, we don't need an ISB here * --------------------------------------------- */ adr x0, runtime_exceptions msr vbar_el3, x0 - /* -------------------------------------------- - * Use the size of the general purpose register - * context to restore the register state - * stashed by earlier code - * -------------------------------------------- - */ - sub sp, sp, #SIZEOF_GPREGS - exception_exit restore_regs - - /* -------------------------------------------- - * Jump back to the non-secure world assuming - * that the elr and spsr setup has been done - * by the finishers - * -------------------------------------------- - */ - eret + zero_callee_saved_regs + b el3_exit _panic: b _panic |