diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2016-04-04 12:34:24 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2016-04-07 16:30:45 +0100 |
| commit | 99e58f9e6943caeee72b3106c2c8a1cc3cdc7bf5 (patch) | |
| tree | d99ce13a2891a11bb714e43349ff4319f85c9a21 /common | |
| parent | 61dbb0285f478dcc0be5eb8c86291e203c9c80c2 (diff) | |
Enable SCR_EL3.SIF bit
This patch enables the SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and
BL31 common architectural setup code. When in secure state, this disables
instruction fetches from Non-secure memory.
NOTE: THIS COULD BREAK PLATFORMS THAT HAVE SECURE WORLD CODE EXECUTING FROM
NON-SECURE MEMORY, BUT THIS IS CONSIDERED UNLIKELY AND IS A SERIOUS SECURITY
RISK.
Fixes ARM-Software/tf-issues#372
Change-Id: I684e84b8d523c3b246e9a5fabfa085b6405df319
Diffstat (limited to 'common')
0 files changed, 0 insertions, 0 deletions