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| author | Soby Mathew <soby.mathew@arm.com> | 2014-09-22 12:15:26 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2014-10-29 17:38:56 +0000 |
| commit | b1a9631d8110a2bcd458ec5809b50d5263a200ef (patch) | |
| tree | 8fd89f21b24dfb9a0b6c00c0aa137547d50cfcd5 /docs/cpu-errata-workarounds.md | |
| parent | 7395a725ae74de70820d7b126ba1af727f39e263 (diff) | |
Optimize barrier usage during Cortex-A57 power down
This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.
Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
Diffstat (limited to 'docs/cpu-errata-workarounds.md')
0 files changed, 0 insertions, 0 deletions