diff options
| author | Juan Castillo <juan.castillo@arm.com> | 2015-12-10 15:49:17 +0000 |
|---|---|---|
| committer | Juan Castillo <juan.castillo@arm.com> | 2015-12-14 12:31:16 +0000 |
| commit | f59821d51255f14e0ac00eef7bc98ef75c686876 (patch) | |
| tree | 2a62aec945a1c30ed695ba2a3336c08d94183ab3 /docs/firmware-design.md | |
| parent | 516beb585c23056820a854b12c77a6f62cbc5c8b (diff) | |
Replace all SCP FW (BL0, BL3-0) references
This patch replaces all references to the SCP Firmware (BL0, BL30,
BL3-0, bl30) with the image terminology detailed in the TF wiki
(https://github.com/ARM-software/arm-trusted-firmware/wiki):
BL0 --> SCP_BL1
BL30, BL3-0 --> SCP_BL2
bl30 --> scp_bl2
This change affects code, documentation, build system, tools and
platform ports that load SCP firmware. ARM plaforms have been
updated to the new porting API.
IMPORTANT: build option to specify the SCP FW image has changed:
BL30 --> SCP_BL2
IMPORTANT: This patch breaks compatibility for platforms that use BL2
to load SCP firmware. Affected platforms must be updated as follows:
BL30_IMAGE_ID --> SCP_BL2_IMAGE_ID
BL30_BASE --> SCP_BL2_BASE
bl2_plat_get_bl30_meminfo() --> bl2_plat_get_scp_bl2_meminfo()
bl2_plat_handle_bl30() --> bl2_plat_handle_scp_bl2()
Change-Id: I24c4c1a4f0e4b9f17c9e4929da815c4069549e58
Diffstat (limited to 'docs/firmware-design.md')
| -rw-r--r-- | docs/firmware-design.md | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 41fb7c0d..51084f45 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -248,16 +248,16 @@ BL2 also initializes a UART (PL011 console), which enables access to the access to controlled components. The storage abstraction layer is initialized which is used to load further bootloader images. -#### BL3-0 (System Control Processor Firmware) image load +#### SCP_BL2 (System Control Processor Firmware) image load Some systems have a separate System Control Processor (SCP) for power, clock, -reset and system control. BL2 loads the optional BL3-0 image from platform +reset and system control. BL2 loads the optional SCP_BL2 image from platform storage into a platform-specific region of secure memory. The subsequent -handling of BL3-0 is platform specific. For example, on the Juno ARM development -platform port the image is transferred into SCP's internal memory using the Boot -Over MHU (BOM) protocol after being loaded in the trusted SRAM memory. The SCP -executes BL3-0 and signals to the Application Processor (AP) for BL2 execution -to continue. +handling of SCP_BL2 is platform specific. For example, on the Juno ARM +development platform port the image is transferred into SCP's internal memory +using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM +memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) +for BL2 execution to continue. #### BL3-1 (EL3 Runtime Firmware) image load @@ -1249,7 +1249,7 @@ The following list describes the memory layout on the ARM development platforms: * BL2 is loaded below BL3-1. -* On Juno, BL3-0 is loaded temporarily into the BL3-1 memory region and +* On Juno, SCP_BL2 is loaded temporarily into the BL3-1 memory region and transfered to the SCP before being overwritten by BL3-1. * BL3-2 can be loaded in one of the following locations: @@ -1356,12 +1356,12 @@ layout of the other images in Trusted SRAM. 0x0BEC0000 |----------| : : 0x08000000 +----------+ BL3-1 is loaded - after BL3-0 has + after SCP_BL2 has Trusted SRAM been sent to SCP 0x04040000 +----------+ loaded by BL2 ------------------ | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | |----------| <<<<<<<<<<<<< |----------------| - | BL3-0 | <<<<<<<<<<<<< | BL3-1 PROGBITS | + | SCP_BL2 | <<<<<<<<<<<<< | BL3-1 PROGBITS | |----------| ------------------ | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | |----------| <<<<<<<<<<<<< |----------------| @@ -1390,12 +1390,12 @@ layout of the other images in Trusted SRAM. 0x0BEC0000 |----------| : : 0x08000000 +----------+ BL3-1 is loaded - after BL3-0 has + after SCP_BL2 has Trusted SRAM been sent to SCP 0x04040000 +----------+ loaded by BL2 ------------------ | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | |----------| <<<<<<<<<<<<< |----------------| - | BL3-0 | <<<<<<<<<<<<< | BL3-1 PROGBITS | + | SCP_BL2 | <<<<<<<<<<<<< | BL3-1 PROGBITS | |----------| ------------------ | BL2 | |----------| |