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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-01-08 14:12:55 +0000 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-01-12 11:19:39 +0000 |
| commit | fcb22cf0f46a75f7c1a50035f5215b7caa1ed4c7 (patch) | |
| tree | 7a0f2213db4d6f51c45f8b3226555e4293d2022e /docs/firmware-design.md | |
| parent | de849c8c4ff36f24cc563a85e6c3121b9842c50b (diff) | |
Documentation: Fix broken links in ToCs
Change-Id: I4fcdb8e813e0392c2cd3d0623698e8319b3b0593
Diffstat (limited to 'docs/firmware-design.md')
| -rw-r--r-- | docs/firmware-design.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 015ffe56..7ae1de32 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -8,7 +8,7 @@ Contents : 3. [EL3 runtime services framework](#3--el3-runtime-services-framework) 4. [Power State Coordination Interface](#4--power-state-coordination-interface) 5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers) -6. [Crash Reporting in BL31](#6--crash-reporting-in-bl3-1) +6. [Crash Reporting in BL31](#6--crash-reporting-in-bl31) 7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers) 8. [CPU specific operations framework](#8--cpu-specific-operations-framework) 9. [Memory layout of BL images](#9-memory-layout-of-bl-images) @@ -1454,8 +1454,8 @@ The ARM development platforms' policy is to only allow loading of a known set of images. The platform policy can be modified to allow additional images. -11. Use of coherent memory in Trusted Firmware ----------------------------------------------- +11. Use of coherent memory in Trusted Firmware +----------------------------------------------- There might be loss of coherency when physical memory with mismatched shareability, cacheability and memory attributes is accessed by multiple CPUs |