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| author | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
| commit | 4ca473db0d60c7b3e67c7ebd5096e41f3dc45bf2 (patch) | |
| tree | 2465dcd7d4c6bee4c9f9ec7c3ef17c71221b3ca3 /docs/user-guide.md | |
| parent | 8d297cc94312c52b5104235fcdc4127ecef6d1af (diff) | |
| parent | 63b8440fcc3954817e20d3ba7a0be74435a284d2 (diff) | |
Merge pull request #456 from soby-mathew/sm/gicv3-tsp-plat-changes-v2
Modify TSP and ARM standard platforms for new GIC drivers v2
Diffstat (limited to 'docs/user-guide.md')
| -rw-r--r-- | docs/user-guide.md | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/docs/user-guide.md b/docs/user-guide.md index bcdc645d..716ed7d8 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -278,10 +278,13 @@ performed. (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1. -* `TSPD_ROUTE_IRQ_TO_EL3`: A non zero value enables the routing model - for non-secure interrupts in which they are routed to EL3 (TSPD). The - default model (when the value is 0) is to route non-secure interrupts - to S-EL1 (TSP). +* `TSP_NS_INTR_ASYNC_PREEMPT`: A non zero value enables the interrupt + routing model which routes non-secure interrupts asynchronously from TSP + to EL3 causing immediate preemption of TSP. The EL3 is responsible + for saving and restoring the TSP context in this routing model. The + default routing model (when the value is 0) is to route non-secure + interrupts to TSP allowing it to save its context and hand over + synchronously to EL3 via an SMC. * `TRUSTED_BOARD_BOOT`: Boolean flag to include support for the Trusted Board Boot feature. When set to '1', BL1 and BL2 images include support to load |