Optimize Cortex-A57 cluster power down sequence on Juno

This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.

This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.

Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480

2 files changed, 36 insertions, 4 deletions

diff --git a/docs/cpu-errata-workarounds.md b/docs/cpu-specific-build-macros.md
index 09f7c72d..246381a8 100644
--- a/docs/cpu-errata-workarounds.md
+++ b/docs/cpu-specific-build-macros.md
@@ -1,5 +1,22 @@
-ARM CPU Errata Workarounds
-==========================
+ARM CPU Specific Build Macros
+=============================
+
+Contents
+--------
+
+1.  Introduction
+2.  CPU Errata Workarounds
+3.  CPU Specific optimizations
+
+1.  Introduction
+----------------
+
+This document describes the various build options present in the CPU specific
+operations framework to enable errata workarounds and to enable optimizations
+for a specific CPU on a platform.
+
+2.  CPU Errata Workarounds
+--------------------------
 
 ARM Trusted Firmware exports a series of build flags which control the
 errata workarounds that are applied to each CPU by the reset handler. The
@@ -33,6 +50,20 @@ For Cortex-A57, following errata build flags are defined :
 *   `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
      CPU. This needs to be enabled only for revision r0p0 of the CPU.
 
+3.  CPU Specific optimizations
+------------------------------
+
+This section describes some of the optimizations allowed by the CPU micro
+architecture that can be enabled by the platform as desired.
+
+*    `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the
+     Cortex-A57 cluster power down sequence by not flushing the Level 1 data
+     cache. The L1 data cache and the L2 unified cache are inclusive. A flush
+     of the L2 by set/way flushes any dirty lines from the L1 as well. This
+     is a known safe deviation from the Cortex-A57 TRM defined power down
+     sequence. Each Cortex-A57 based platform must make its own decision on
+     whether to use the optimization.
+
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
 _Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._
diff --git a/docs/firmware-design.md b/docs/firmware-design.md
index fde61da7..bc075da3 100644
--- a/docs/firmware-design.md
+++ b/docs/firmware-design.md
@@ -982,9 +982,10 @@ Please note that only 2. is mandated by the TRM.
 
 The CPU specific operations framework scales to accommodate a large number of
 different CPUs during power down and reset handling. The platform can specify
+any CPU optimization it wants to enable for each CPU. It can also specify
 the CPU errata workarounds to be applied for each CPU type during reset
 handling by defining CPU errata compile time macros. Details on these macros
-can be found in the [cpu-errata-workarounds.md][ERRW] file.
+can be found in the [cpu-specific-build-macros.md][CPUBM] file.
 
 The CPU specific operations framework depends on the `cpu_ops` structure which
 needs to be exported for each type of CPU in the platform. It is defined in
@@ -1485,4 +1486,4 @@ _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
 [User Guide]:       ./user-guide.md
 [Porting Guide]:    ./porting-guide.md
 [INTRG]:            ./interrupt-framework-design.md
-[ERRW]:             ./cpu-errata-workarounds.md
+[CPUBM]:            ./cpu-specific-build-macros.md.md