diff options
| author | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
| commit | 4ca473db0d60c7b3e67c7ebd5096e41f3dc45bf2 (patch) | |
| tree | 2465dcd7d4c6bee4c9f9ec7c3ef17c71221b3ca3 /include/bl31/interrupt_mgmt.h | |
| parent | 8d297cc94312c52b5104235fcdc4127ecef6d1af (diff) | |
| parent | 63b8440fcc3954817e20d3ba7a0be74435a284d2 (diff) | |
Merge pull request #456 from soby-mathew/sm/gicv3-tsp-plat-changes-v2
Modify TSP and ARM standard platforms for new GIC drivers v2
Diffstat (limited to 'include/bl31/interrupt_mgmt.h')
| -rw-r--r-- | include/bl31/interrupt_mgmt.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index e07ddf83..0172b607 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -63,6 +63,10 @@ #define INTR_NS_VALID_RM0 0x0 /* Routed to EL1/EL2 from NS and to EL3 from Secure */ #define INTR_NS_VALID_RM1 0x1 +/* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ +#define INTR_EL3_VALID_RM0 0x2 +/* Routed to EL3 from NS and Secure */ +#define INTR_EL3_VALID_RM1 0x3 /* This is the default routing model */ #define INTR_DEFAULT_RM 0x0 @@ -87,12 +91,16 @@ * of interrupt. If the model does not match one of the valid masks * -EINVAL is returned. ******************************************************************************/ -#define validate_sel1_interrupt_rm(x) (x == INTR_SEL1_VALID_RM0 ? 0 : \ - (x == INTR_SEL1_VALID_RM1 ? 0 :\ +#define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \ + ((x) == INTR_SEL1_VALID_RM1 ? 0 :\ + -EINVAL)) + +#define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \ + ((x) == INTR_NS_VALID_RM1 ? 0 :\ -EINVAL)) -#define validate_ns_interrupt_rm(x) (x == INTR_NS_VALID_RM0 ? 0 : \ - (x == INTR_NS_VALID_RM1 ? 0 :\ +#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \ + ((x) == INTR_EL3_VALID_RM1 ? 0 :\ -EINVAL)) /******************************************************************************* |