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| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-04-25 10:49:30 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-07 11:32:25 +0100 |
| commit | 5f6032a8206bb88655367f96cc1270525bed9e48 (patch) | |
| tree | aca93bb3c4778253a238bc41b603a8760aee9783 /include/common/asm_macros.S | |
| parent | e404d7f44a190b82332bb96daffa0c6239732218 (diff) | |
Optimise data cache clean/invalidate operation
The data cache clean and invalidate operations dcsw_op_all()
and dcsw_op_loius() were implemented to invoke a DSB and ISB
barrier for every set/way operation. This adds a substantial
performance penalty to an already expensive operation.
These functions have been reworked to provide an optimised
implementation derived from the code in section D3.4 of the
ARMv8 ARM. The helper macro setup_dcsw_op_args has been moved
and reworked alongside the implementation.
Fixes ARM-software/tf-issues#146
Change-Id: Icd5df57816a83f0a842fce935320a369f7465c7f
Diffstat (limited to 'include/common/asm_macros.S')
| -rw-r--r-- | include/common/asm_macros.S | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S index 6cf1a19f..3edd3921 100644 --- a/include/common/asm_macros.S +++ b/include/common/asm_macros.S @@ -65,13 +65,6 @@ .endm - .macro setup_dcsw_op_args start_level, end_level, clidr, shift, fw, ls - mrs \clidr, clidr_el1 - mov \start_level, xzr - ubfx \end_level, \clidr, \shift, \fw - lsl \end_level, \end_level, \ls - .endm - /* * This macro verifies that the a given vector doesn't exceed the * architectural limit of 32 instructions. This is meant to be placed |