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| author | Dan Handley <dan.handley@arm.com> | 2015-03-30 17:15:16 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2015-04-27 18:05:06 +0100 |
| commit | ce4c820d8ccf803dac0329cabdd6e75c78e81f4e (patch) | |
| tree | 65ec4e21ba293bc53bc58c182805e05e0873918f /include/common/assert_macros.S | |
| parent | 1b70db06ff8dcd34c4d6ad5a3499f602318d376d (diff) | |
Remove use of PLATFORM_CACHE_LINE_SIZE
The required platform constant PLATFORM_CACHE_LINE_SIZE is
unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the
same information. CACHE_WRITEBACK_GRANULE is preferred since this
is an architecturally defined term and allows comparison with the
corresponding hardware register value.
Replace all usage of PLATFORM_CACHE_LINE_SIZE with
CACHE_WRITEBACK_GRANULE.
Also, add a runtime assert in BL1 to check that the provided
CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0.
Change-Id: If87286be78068424217b9f3689be358356500dcd
Diffstat (limited to 'include/common/assert_macros.S')
0 files changed, 0 insertions, 0 deletions