diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-07-17 16:06:39 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2014-08-21 14:53:48 +0100 |
| commit | 01b916bff2dca219d4088b8abca0a02ac06dd615 (patch) | |
| tree | 0443c312a8bf35a8aa3a53b76096e830e11c4f7c /include/lib | |
| parent | e822d7c1c7c2c7bf45084138d8a504bf8ebe0b36 (diff) | |
Juno: Implement initial platform port
This patch adds the initial port of the ARM Trusted Firmware on the Juno
development platform. This port does not support a BL3-2 image or any PSCI APIs
apart from PSCI_VERSION and PSCI_CPU_ON. It enables workarounds for selected
Cortex-A57 (#806969 & #813420) errata and implements the workaround for a Juno
platform errata (Defect id 831273).
Change-Id: Ib3d92df3af53820cfbb2977582ed0d7abf6ef893
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch64/arch.h | 4 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 11 |
2 files changed, 15 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index b2aac2fb..40562607 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -166,6 +166,10 @@ #define EL0VTEN_BIT (1 << 8) #define EL0PCTEN_BIT (1 << 0) #define EL0VCTEN_BIT (1 << 1) +#define EVNTEN_BIT (1 << 2) +#define EVNTDIR_BIT (1 << 3) +#define EVNTI_SHIFT 4 +#define EVNTI_MASK 0xf /* CPTR_EL3 definitions */ #define TCPAC_BIT (1 << 31) diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 9cf8780d..6128b169 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -52,4 +52,15 @@ #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ + +#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 + +#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 + #endif /* __CORTEX_A57_H__ */ |