diff options
| author | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-06-28 16:58:26 +0100 |
|---|---|---|
| committer | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-09-21 16:27:15 +0100 |
| commit | 1a0a3f0622e4b569513304109d9a0d093b71228a (patch) | |
| tree | 9850566923168a92a6ec7ebbabe03119f14b2786 /include/lib | |
| parent | a8aa7fec1d4a6df8617c0d0463f1e10f1827a609 (diff) | |
AArch32: Common changes needed for BL1/BL2
This patch adds common changes to support AArch32 state in
BL1 and BL2. Following are the changes:
* Added functions for disabling MMU from Secure state.
* Added AArch32 specific SMC function.
* Added semihosting support.
* Added reporting of unhandled exceptions.
* Added uniprocessor stack support.
* Added `el3_entrypoint_common` macro that can be
shared by BL1 and BL32 (SP_MIN) BL stages. The
`el3_entrypoint_common` is similar to the AArch64
counterpart with the main difference in the assembly
instructions and the registers that are relevant to
AArch32 execution state.
* Enabled `LOAD_IMAGE_V2` flag in Makefile for
`ARCH=aarch32` and added check to make sure that
platform has not overridden to disable it.
Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch32/arch.h | 1 | ||||
| -rw-r--r-- | include/lib/aarch32/arch_helpers.h | 8 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cpu_macros.S | 8 |
3 files changed, 17 insertions, 0 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 6653cd14..aba15df1 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -191,6 +191,7 @@ /* NASCR definitions */ #define NSASEDIS_BIT (1 << 15) +#define NSTRCDIS_BIT (1 << 20) #define NASCR_CP11_BIT (1 << 11) #define NASCR_CP10_BIT (1 << 10) diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index ddf660b1..3b4349c3 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -187,6 +187,9 @@ void flush_dcache_range(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); +void disable_mmu_secure(void); +void disable_mmu_icache_secure(void); + DEFINE_SYSOP_FUNC(wfi) DEFINE_SYSOP_FUNC(wfe) DEFINE_SYSOP_FUNC(sev) @@ -196,6 +199,9 @@ DEFINE_SYSOP_TYPE_FUNC(dsb, ish) DEFINE_SYSOP_TYPE_FUNC(dmb, ish) DEFINE_SYSOP_FUNC(isb) +void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3, + uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7); + DEFINE_SYSREG_RW_FUNCS(spsr) DEFINE_SYSREG_RW_FUNCS(cpsr) @@ -289,4 +295,6 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) #define read_cntpct_el0() read64_cntpct() +#define read_ctr_el0() read_ctr() + #endif /* __ARCH_HELPERS_H__ */ diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index f58f3e94..2b9947e3 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S @@ -42,12 +42,16 @@ CPU_MIDR: /* cpu_ops midr */ .space 4 /* Reset fn is needed during reset */ +#if IMAGE_BL1 || IMAGE_BL32 CPU_RESET_FUNC: /* cpu_ops reset_func */ .space 4 +#endif +#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */ CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ .space 4 CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ .space 4 +#endif CPU_OPS_SIZE = . /* @@ -60,13 +64,17 @@ CPU_OPS_SIZE = . .align 2 .type cpu_ops_\_name, %object .word \_midr +#if IMAGE_BL1 || IMAGE_BL32 .if \_noresetfunc .word 0 .else .word \_name\()_reset_func .endif +#endif +#if IMAGE_BL32 .word \_name\()_core_pwr_dwn .word \_name\()_cluster_pwr_dwn +#endif .endm #endif /* __CPU_MACROS_S__ */ |