diff options
| author | Jimmy Huang <jimmy.huang@mediatek.com> | 2015-07-29 20:55:31 +0800 |
|---|---|---|
| committer | Yidi Lin <yidi.lin@mediatek.com> | 2015-08-05 19:58:39 +0800 |
| commit | 6b0d97b24a9414b754e9531cba7275438d5f77be (patch) | |
| tree | ee1046e1b8fb6c0535ca92ae0e9881686a226ab2 /include/lib | |
| parent | fd904df14b1ab4304bd02c00f82f0c6888f8e7a8 (diff) | |
cortex_a53: Add A53 errata #826319, #836870
- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added errata build flags
Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 14821ab6..6e71f9ca 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -41,4 +41,19 @@ #define CPUECTLR_SMP_BIT (1 << 6) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_DTAH (1 << 24) + +/******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define L2ACTLR_EL1 S3_1_C15_C0_0 /* Instruction def. */ + +#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) +#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) + #endif /* __CORTEX_A53_H__ */ |