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| author | Soby Mathew <soby.mathew@arm.com> | 2014-09-22 12:11:36 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2014-10-29 17:38:56 +0000 |
| commit | 7395a725ae74de70820d7b126ba1af727f39e263 (patch) | |
| tree | 495f724c1b155df73528758037e068b51827e949 /include/lib | |
| parent | 8e85791677a334bc7ed0799b18adad91ef3c1db4 (diff) | |
Apply errata workarounds only when major/minor revisions match.
Prior to this patch, the errata workarounds were applied for any version
of the CPU in the release build and in the debug build an assert
failure resulted when the revision did not match. This patch applies
errata workarounds in the Cortex-A57 reset handler only if the 'variant'
and 'revision' fields read from the MIDR_EL1 match. In the debug build,
a warning message is printed for each errata workaround which is not
applied.
The patch modifies the register usage in 'reset_handler` so
as to adhere to ARM procedure calling standards.
Fixes ARM-software/tf-issues#242
Change-Id: I51b1f876474599db885afa03346e38a476f84c29
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch64/arch.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index e5b2bf8c..476c9c5c 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -38,7 +38,9 @@ #define MIDR_IMPL_MASK 0xff #define MIDR_IMPL_SHIFT 0x18 #define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_BITS 4 #define MIDR_REV_SHIFT 0 +#define MIDR_REV_BITS 4 #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 |