diff options
| author | Dan Handley <dan.handley@arm.com> | 2015-03-30 17:15:16 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2015-04-27 18:05:06 +0100 |
| commit | ce4c820d8ccf803dac0329cabdd6e75c78e81f4e (patch) | |
| tree | 65ec4e21ba293bc53bc58c182805e05e0873918f /include/lib | |
| parent | 1b70db06ff8dcd34c4d6ad5a3499f602318d376d (diff) | |
Remove use of PLATFORM_CACHE_LINE_SIZE
The required platform constant PLATFORM_CACHE_LINE_SIZE is
unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the
same information. CACHE_WRITEBACK_GRANULE is preferred since this
is an architecturally defined term and allows comparison with the
corresponding hardware register value.
Replace all usage of PLATFORM_CACHE_LINE_SIZE with
CACHE_WRITEBACK_GRANULE.
Also, add a runtime assert in BL1 to check that the provided
CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0.
Change-Id: If87286be78068424217b9f3689be358356500dcd
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch64/arch.h | 19 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 4 |
2 files changed, 21 insertions, 2 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 5e216737..912643d2 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -302,6 +302,23 @@ ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) +/* + * CTR_EL0 definitions + */ +#define CTR_CWG_SHIFT 24 +#define CTR_CWG_MASK 0xf +#define CTR_ERG_SHIFT 20 +#define CTR_ERG_MASK 0xf +#define CTR_DMINLINE_SHIFT 16 +#define CTR_DMINLINE_MASK 0xf +#define CTR_L1IP_SHIFT 14 +#define CTR_L1IP_MASK 0x3 +#define CTR_IMINLINE_SHIFT 0 +#define CTR_IMINLINE_MASK 0xf + +#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +#define SIZE_FROM_LOG2_WORDS(n) (4 << (n)) + /* Physical timer control register bit fields shifts and masks */ #define CNTP_CTL_ENABLE_SHIFT 0 diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index ceb88e47..b7ab3da6 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -281,6 +281,8 @@ DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) DEFINE_SYSREG_READ_FUNC(isr_el1) +DEFINE_SYSREG_READ_FUNC(ctr_el0) + /* GICv3 System Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) |