diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2014-08-14 13:36:41 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-08-20 19:14:31 +0100 |
| commit | d3f70af6e09d669da9c7d7890b7af5a0cdc4b3a5 (patch) | |
| tree | 30c78c0c34a461ddc00ec1d1828ea5c53abbeb8d /include/lib | |
| parent | add403514d0f792b9df3c81006cd9a9395b213f6 (diff) | |
Add CPU specific crash reporting handlers
This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register
state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are
dumped currently.
Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch64/arch.h | 8 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cpu_macros.S | 7 |
4 files changed, 11 insertions, 8 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 333dcf1d..97242ccb 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -39,9 +39,6 @@ #define MIDR_IMPL_SHIFT 0x18 #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 -#define MIDR_PN_AEM 0xd0f -#define MIDR_PN_A57 0xd07 -#define MIDR_PN_A53 0xd03 /******************************************************************************* * MPIDR macros @@ -77,11 +74,6 @@ #define ICC_PMR_EL1 S3_0_C4_C6_0 /******************************************************************************* - * Implementation defined sysreg encodings - ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 - -/******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF 0x000 diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index dcae411e..14821ab6 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -37,6 +37,8 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + #define CPUECTLR_SMP_BIT (1 << 6) #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index cf887d00..dc0e0f4e 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -37,6 +37,8 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + #define CPUECTLR_SMP_BIT (1 << 6) #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index abe8973f..65fb82d6 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -50,6 +50,10 @@ CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ .space 8 #endif +#if (IMAGE_BL31 && CRASH_REPORTING) +CPU_REG_DUMP: /* cpu specific register dump for crash reporting */ + .space 8 +#endif CPU_OPS_SIZE = . /* @@ -72,4 +76,7 @@ CPU_OPS_SIZE = . .quad \_name\()_core_pwr_dwn .quad \_name\()_cluster_pwr_dwn #endif +#if (IMAGE_BL31 && CRASH_REPORTING) + .quad \_name\()_cpu_reg_dump +#endif .endm |