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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-14 13:32:31 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-21 09:44:51 +0100 |
| commit | df22d602b6b1ee00a0cb31e88bb63e7152f2cf6a (patch) | |
| tree | 75145b1bc05af5e40dc3924f5c2658cf1acaf623 /include/lib | |
| parent | 097b787a0e6dc65ff4bf7c6e1da966858036e22a (diff) | |
Add support for Cortex-A57 erratum 826974 workaround
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c512129a..7711e690 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -61,6 +61,7 @@ ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ +#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) |