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| author | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
| commit | 4ca473db0d60c7b3e67c7ebd5096e41f3dc45bf2 (patch) | |
| tree | 2465dcd7d4c6bee4c9f9ec7c3ef17c71221b3ca3 /include/plat/arm/common/arm_def.h | |
| parent | 8d297cc94312c52b5104235fcdc4127ecef6d1af (diff) | |
| parent | 63b8440fcc3954817e20d3ba7a0be74435a284d2 (diff) | |
Merge pull request #456 from soby-mathew/sm/gicv3-tsp-plat-changes-v2
Modify TSP and ARM standard platforms for new GIC drivers v2
Diffstat (limited to 'include/plat/arm/common/arm_def.h')
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 4726d5e5..5c03feb9 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -135,6 +135,22 @@ #define ARM_IRQ_SEC_SGI_6 14 #define ARM_IRQ_SEC_SGI_7 15 +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ + ARM_IRQ_SEC_SGI_1, \ + ARM_IRQ_SEC_SGI_2, \ + ARM_IRQ_SEC_SGI_3, \ + ARM_IRQ_SEC_SGI_4, \ + ARM_IRQ_SEC_SGI_5, \ + ARM_IRQ_SEC_SGI_7 + +#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ + ARM_IRQ_SEC_SGI_6 + #define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ MT_MEMORY : MT_DEVICE) \ | MT_RW | MT_SECURE) |