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| author | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2015-12-09 10:41:08 +0000 |
| commit | 4ca473db0d60c7b3e67c7ebd5096e41f3dc45bf2 (patch) | |
| tree | 2465dcd7d4c6bee4c9f9ec7c3ef17c71221b3ca3 /include/plat/arm/css/common/css_def.h | |
| parent | 8d297cc94312c52b5104235fcdc4127ecef6d1af (diff) | |
| parent | 63b8440fcc3954817e20d3ba7a0be74435a284d2 (diff) | |
Merge pull request #456 from soby-mathew/sm/gicv3-tsp-plat-changes-v2
Modify TSP and ARM standard platforms for new GIC drivers v2
Diffstat (limited to 'include/plat/arm/css/common/css_def.h')
| -rw-r--r-- | include/plat/arm/css/common/css_def.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 98b69cb3..99491f88 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -61,6 +61,16 @@ #define CSS_IRQ_SEC_SYS_TIMER 91 /* + * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a + * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. + */ +#define CSS_G1S_IRQS CSS_IRQ_MHU, \ + CSS_IRQ_GPU_SMMU_0, \ + CSS_IRQ_TZC, \ + CSS_IRQ_TZ_WDOG, \ + CSS_IRQ_SEC_SYS_TIMER + +/* * SCP <=> AP boot configuration * * The SCP/AP boot configuration is a 32-bit word located at a known offset from |