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| author | Soby Mathew <soby.mathew@arm.com> | 2016-07-26 17:46:56 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2016-07-27 10:46:09 +0100 |
| commit | 61e30277199e5457483bef791cb5bc026c402a1f (patch) | |
| tree | 0ac84a44f665d3ededfaeb5a6785315f29869809 /include | |
| parent | 3dd9835f8ab3c2e7f57ddc92505d6c800bbacd47 (diff) | |
GICv3: Fix the GICD_IROUTER offset
This patch fixes the offset of GICD_IROUTER register defined in gicv3.h.
Although the GICv3 documention mentions that the offset for this register
is 0x6100-0x7FD8, the offset calculation for an interrupt id `n` is :
0x6000 + 8n, where n >= 32
This requires the offset for GICD_IROUTER to be defined as 0x6000.
Fixes ARM-software/tf-issues#410
Change-Id: If9e91e30d946afe7f1f60fea4f065c7567093fa8
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/arm/gicv3.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index e915c072..b7ad7785 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -55,7 +55,11 @@ #define GICD_SETSPI_SR 0x50 #define GICD_CLRSPI_SR 0x50 #define GICD_IGRPMODR 0xd00 -#define GICD_IROUTER 0x6100 +/* + * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and + * n >= 32, making the effective offset as 0x6100. + */ +#define GICD_IROUTER 0x6000 #define GICD_PIDR2_GICV3 0xffe8 #define IGRPMODR_SHIFT 5 |