diff options
| author | danh-arm <dan.handley@arm.com> | 2016-04-07 17:17:25 +0100 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2016-04-07 17:17:25 +0100 |
| commit | 7a0ae2f457d4d80daa94c357254fee757337ff28 (patch) | |
| tree | 8955b127ac5df141729483f6486739e555a21094 /include | |
| parent | 0892f6b60568594cba2435365abd486e58eadf77 (diff) | |
| parent | 99e58f9e6943caeee72b3106c2c8a1cc3cdc7bf5 (diff) | |
Merge pull request #584 from soby-mathew/sm/enable_scr_sif
Enable SCR_EL3.SIF bit
Diffstat (limited to 'include')
| -rw-r--r-- | include/common/el3_common_macros.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S index ba80d95d..9b22a734 100644 --- a/include/common/el3_common_macros.S +++ b/include/common/el3_common_macros.S @@ -70,11 +70,12 @@ isb /* --------------------------------------------------------------------- - * Early set RES1 bits in SCR_EL3. Set EA bit as well to catch both - * External Aborts and SError Interrupts in EL3. + * Early set RES1 bits in SCR_EL3. Set EA bit to catch both + * External Aborts and SError Interrupts in EL3 and also the SIF bit + * to disable instruction fetches from Non-secure memory. * --------------------------------------------------------------------- */ - mov x0, #(SCR_RES1_BITS | SCR_EA_BIT) + mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT) msr scr_el3, x0 /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception |