diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2015-11-25 17:00:44 +0000 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2015-12-09 11:34:10 +0000 |
| commit | 85d80e557803a8f3e966a0b58dc036aa8c33f153 (patch) | |
| tree | 52ccd1adfc3362a4259bfe07da725d6a0a135587 /include | |
| parent | 05a91fb008c31f939a9590318e2914b44cdad165 (diff) | |
Initialize VTTBR_EL2 when bypassing EL2
In the situation that EL1 is selected as the exception level for the
next image upon BL31 exit for a processor that supports EL2, the
context management code must configure all essential EL2 register
state to ensure correct execution of EL1.
VTTBR_EL2 should be part of this set of EL2 registers because:
- The ARMv8-A architecture does not define a reset value for this
register.
- Cache maintenance operations depend on VTTBR_EL2.VMID even when
non-secure EL1&0 stage 2 address translation are disabled.
This patch initializes the VTTBR_EL2 register to 0 when bypassing EL2
to address this issue. Note that this bug has not yet manifested
itself on FVP or Juno because VTTBR_EL2.VMID resets to 0 on the
Cortex-A53 and Cortex-A57.
Change-Id: I58ce2d16a71687126f437577a506d93cb5eecf33
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 43c6917e..067b8302 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -270,6 +270,8 @@ DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) +DEFINE_SYSREG_RW_FUNCS(vttbr_el2) + DEFINE_SYSREG_RW_FUNCS(cptr_el2) DEFINE_SYSREG_RW_FUNCS(cptr_el3) |