diff options
| author | danh-arm <dan.handley@arm.com> | 2016-07-15 18:14:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-07-15 18:14:41 +0100 |
| commit | e254e3fad41164ed421b22a9bcd9b918c54490c1 (patch) | |
| tree | 09cf01b48d5234c0576bdb846c7238aac574af9b /include | |
| parent | 32bc641dc10287fbaef5c1dfe5e34ff12cc8dbbf (diff) | |
| parent | 84629f2f2cf73b6d6180fc8a234f1ea9d423b280 (diff) | |
Merge pull request #655 from Xilinx/report_merr
bl31: Add error reporting registers
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a73.h | 5 |
4 files changed, 35 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 169d8f4b..6976b809 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -57,6 +57,11 @@ #define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -79,4 +84,9 @@ #define L2ECTLR_RET_CTRL_SHIFT 0 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index ac4ae570..c5a218b7 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -57,6 +57,11 @@ #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -90,4 +95,9 @@ #define L2ECTLR_RET_CTRL_SHIFT 0 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index fa10ca90..01edf43b 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -45,6 +45,11 @@ #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -65,4 +70,9 @@ #define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 2ad04677..13e114a3 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -41,4 +41,9 @@ #define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A73_H__ */ |