Merge pull request #284 from kpet/kp/tf-issues-295

Add support to indicate size and end of assembly functions

5 files changed, 35 insertions, 0 deletions

diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 58a64a6c..ee53058e 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -49,6 +49,7 @@ func aem_generic_core_pwr_dwn
 	 * ---------------------------------------------
 	 */
 	b	dcsw_op_louis
+endfunc aem_generic_core_pwr_dwn
 
 
 func aem_generic_cluster_pwr_dwn
@@ -67,6 +68,7 @@ func aem_generic_cluster_pwr_dwn
 	 */
 	mov	x0, #DCCISW
 	b	dcsw_op_all
+endfunc aem_generic_cluster_pwr_dwn
 
 	/* ---------------------------------------------
 	 * This function provides cpu specific
@@ -80,6 +82,7 @@ func aem_generic_cluster_pwr_dwn
 func aem_generic_cpu_reg_dump
 	mov	x6, #0 /* no registers to report */
 	ret
+endfunc aem_generic_cpu_reg_dump
 
 
 /* cpu_ops for Base AEM FVP */
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 188f3c1e..e149e6e6 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -44,6 +44,7 @@ func cortex_a53_disable_dcache
 	msr	sctlr_el3, x1
 	isb
 	ret
+endfunc cortex_a53_disable_dcache
 
 	/* ---------------------------------------------
 	 * Disable intra-cluster coherency
@@ -56,6 +57,7 @@ func cortex_a53_disable_smp
 	isb
 	dsb	sy
 	ret
+endfunc cortex_a53_disable_smp
 
 func cortex_a53_reset_func
 	/* ---------------------------------------------
@@ -72,6 +74,7 @@ func cortex_a53_reset_func
 	isb
 skip_smp_setup:
 	ret
+endfunc cortex_a53_reset_func
 
 func cortex_a53_core_pwr_dwn
 	mov	x18, x30
@@ -95,6 +98,7 @@ func cortex_a53_core_pwr_dwn
 	 */
 	mov	x30, x18
 	b	cortex_a53_disable_smp
+endfunc cortex_a53_core_pwr_dwn
 
 func cortex_a53_cluster_pwr_dwn
 	mov	x18, x30
@@ -131,6 +135,7 @@ func cortex_a53_cluster_pwr_dwn
 	 */
 	mov	x30, x18
 	b	cortex_a53_disable_smp
+endfunc cortex_a53_cluster_pwr_dwn
 
 	/* ---------------------------------------------
 	 * This function provides cortex_a53 specific
@@ -149,5 +154,6 @@ func cortex_a53_cpu_reg_dump
 	adr	x6, cortex_a53_regs
 	mrs	x8, CPUECTLR_EL1
 	ret
+endfunc cortex_a53_cpu_reg_dump
 
 declare_cpu_ops cortex_a53, CORTEX_A53_MIDR
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index eb6c736f..05799d61 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -45,6 +45,7 @@ func cortex_a57_disable_dcache
 	msr	sctlr_el3, x1
 	isb
 	ret
+endfunc cortex_a57_disable_dcache
 
 	/* ---------------------------------------------
 	 * Disable all types of L2 prefetches.
@@ -60,6 +61,7 @@ func cortex_a57_disable_l2_prefetch
 	isb
 	dsb	ish
 	ret
+endfunc cortex_a57_disable_l2_prefetch
 
 	/* ---------------------------------------------
 	 * Disable intra-cluster coherency
@@ -70,6 +72,7 @@ func cortex_a57_disable_smp
 	bic	x0, x0, #CPUECTLR_SMP_BIT
 	msr	CPUECTLR_EL1, x0
 	ret
+endfunc cortex_a57_disable_smp
 
 	/* ---------------------------------------------
 	 * Disable debug interfaces
@@ -81,6 +84,7 @@ func cortex_a57_disable_ext_debug
 	isb
 	dsb	sy
 	ret
+endfunc cortex_a57_disable_ext_debug
 
 	/* --------------------------------------------------
 	 * Errata Workaround for Cortex A57 Errata #806969.
@@ -113,6 +117,7 @@ apply_806969:
 	msr	CPUACTLR_EL1, x1
 skip_806969:
 	ret
+endfunc errata_a57_806969_wa
 
 
 	/* ---------------------------------------------------
@@ -146,6 +151,7 @@ apply_813420:
 	msr	CPUACTLR_EL1, x1
 skip_813420:
 	ret
+endfunc errata_a57_813420_wa
 
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A57.
@@ -188,6 +194,7 @@ func cortex_a57_reset_func
 skip_smp_setup:
 	isb
 	ret	x19
+endfunc cortex_a57_reset_func
 
 	/* ----------------------------------------------------
 	 * The CPU Ops core power down function for Cortex-A57.
@@ -227,6 +234,7 @@ func cortex_a57_core_pwr_dwn
 	 */
 	mov	x30, x18
 	b	cortex_a57_disable_ext_debug
+endfunc cortex_a57_core_pwr_dwn
 
 	/* -------------------------------------------------------
 	 * The CPU Ops cluster power down function for Cortex-A57.
@@ -280,6 +288,7 @@ func cortex_a57_cluster_pwr_dwn
 	 */
 	mov	x30, x18
 	b	cortex_a57_disable_ext_debug
+endfunc cortex_a57_cluster_pwr_dwn
 
 	/* ---------------------------------------------
 	 * This function provides cortex_a57 specific
@@ -298,6 +307,7 @@ func cortex_a57_cpu_reg_dump
 	adr	x6, cortex_a57_regs
 	mrs	x8, CPUECTLR_EL1
 	ret
+endfunc cortex_a57_cpu_reg_dump
 
 
 declare_cpu_ops cortex_a57, CORTEX_A57_MIDR
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index 2d054fcc..eb37f2ca 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -44,6 +44,7 @@ func cortex_a72_disable_dcache
 	msr	sctlr_el3, x1
 	isb
 	ret
+endfunc cortex_a72_disable_dcache
 
 	/* ---------------------------------------------
 	 * Disable all types of L2 prefetches.
@@ -58,6 +59,7 @@ func cortex_a72_disable_l2_prefetch
 	msr	CPUECTLR_EL1, x0
 	isb
 	ret
+endfunc cortex_a72_disable_l2_prefetch
 
 	/* ---------------------------------------------
 	 * Disable the load-store hardware prefetcher.
@@ -70,6 +72,7 @@ func cortex_a72_disable_hw_prefetcher
 	isb
 	dsb	ish
 	ret
+endfunc cortex_a72_disable_hw_prefetcher
 
 	/* ---------------------------------------------
 	 * Disable intra-cluster coherency
@@ -80,6 +83,7 @@ func cortex_a72_disable_smp
 	bic	x0, x0, #CPUECTLR_SMP_BIT
 	msr	CPUECTLR_EL1, x0
 	ret
+endfunc cortex_a72_disable_smp
 
 	/* ---------------------------------------------
 	 * Disable debug interfaces
@@ -91,6 +95,7 @@ func cortex_a72_disable_ext_debug
 	isb
 	dsb	sy
 	ret
+endfunc cortex_a72_disable_ext_debug
 
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A72.
@@ -106,6 +111,7 @@ func cortex_a72_reset_func
 	msr	CPUECTLR_EL1, x0
 	isb
 	ret
+endfunc cortex_a72_reset_func
 
 	/* ----------------------------------------------------
 	 * The CPU Ops core power down function for Cortex-A72.
@@ -151,6 +157,7 @@ func cortex_a72_core_pwr_dwn
 	 */
 	mov	x30, x18
 	b	cortex_a72_disable_ext_debug
+endfunc cortex_a72_core_pwr_dwn
 
 	/* -------------------------------------------------------
 	 * The CPU Ops cluster power down function for Cortex-A72.
@@ -211,6 +218,7 @@ func cortex_a72_cluster_pwr_dwn
 	 */
 	mov	x30, x18
 	b	cortex_a72_disable_ext_debug
+endfunc cortex_a72_cluster_pwr_dwn
 
 	/* ---------------------------------------------
 	 * This function provides cortex_a72 specific
@@ -229,6 +237,7 @@ func cortex_a72_cpu_reg_dump
 	adr	x6, cortex_a72_regs
 	mrs	x8, CPUECTLR_EL1
 	ret
+endfunc cortex_a72_cpu_reg_dump
 
 
 declare_cpu_ops cortex_a72, CORTEX_A72_MIDR
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 24c283ab..e8a13929 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -67,6 +67,7 @@ func reset_handler
 	br	x2
 1:
 	ret
+endfunc reset_handler
 
 #endif /* IMAGE_BL1 || IMAGE_BL31 */
 
@@ -88,6 +89,7 @@ func prepare_core_pwr_dwn
 	/* Get the cpu_ops core_pwr_dwn handler */
 	ldr	x1, [x0, #CPU_PWR_DWN_CORE]
 	br	x1
+endfunc prepare_core_pwr_dwn
 
 	/*
 	 * The prepare cluster power down function for all platforms.  After
@@ -106,6 +108,7 @@ func prepare_cluster_pwr_dwn
 	/* Get the cpu_ops cluster_pwr_dwn handler */
 	ldr	x1, [x0, #CPU_PWR_DWN_CLUSTER]
 	br	x1
+endfunc prepare_cluster_pwr_dwn
 
 
 	/*
@@ -129,6 +132,7 @@ func init_cpu_ops
 	mov x30, x10
 1:
 	ret
+endfunc init_cpu_ops
 #endif /* IMAGE_BL31 */
 
 #if IMAGE_BL31 && CRASH_REPORTING
@@ -153,6 +157,7 @@ func do_cpu_reg_dump
 1:
 	mov	x30, x16
 	ret
+endfunc do_cpu_reg_dump
 #endif
 
 	/*
@@ -197,6 +202,7 @@ func get_cpu_ops_ptr
 	sub	x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
 error_exit:
 	ret
+endfunc get_cpu_ops_ptr
 
 #if DEBUG
 	/*
@@ -221,5 +227,6 @@ func print_revision_warning
 	bl	asm_print_str
 1:
 	ret	x5
+endfunc print_revision_warning
 #endif