diff options
| author | Vikram Kanigiri <vikram.kanigiri@arm.com> | 2015-01-29 18:27:38 +0000 |
|---|---|---|
| committer | Vikram Kanigiri <vikram.kanigiri@arm.com> | 2015-03-13 10:38:09 +0000 |
| commit | 12e7c4ab0bbc9d9d4e950bdbda5a86f61c13bc1a (patch) | |
| tree | b8a888b28f2df72aaae1b759fa3c3c74c8693a2a /lib | |
| parent | 5930eadbe5d8d4c3f15fd910476f72cd5bf86f44 (diff) | |
Initialise cpu ops after enabling data cache
The cpu-ops pointer was initialized before enabling the data cache in the cold
and warm boot paths. This required a DCIVAC cache maintenance operation to
invalidate any stale cache lines resident in other cpus.
This patch moves this initialization to the bl31_arch_setup() function
which is always called after the data cache and MMU has been enabled.
This change removes the need:
1. for the DCIVAC cache maintenance operation.
2. to initialise the CPU ops upon resumption from a PSCI CPU_SUSPEND
call since memory contents are always preserved in this case.
Change-Id: Ibb2fa2f7460d1a1f1e721242025e382734c204c6
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index bebe7c0a..24c283ab 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -110,7 +110,8 @@ func prepare_cluster_pwr_dwn /* * Initializes the cpu_ops_ptr if not already initialized - * in cpu_data. This can be called without a runtime stack. + * in cpu_data. This can be called without a runtime stack, but may + * only be called after the MMU is enabled. * clobbers: x0 - x6, x10 */ .globl init_cpu_ops @@ -125,18 +126,6 @@ func init_cpu_ops ASM_ASSERT(ne) #endif str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! - - /* - * Make sure that any pre-fetched cache copies are invalidated. - * Ensure that we are running with cache disable else we - * invalidate our own update. - */ -#if ASM_ASSERTION - mrs x1, sctlr_el3 - tst x1, #SCTLR_C_BIT - ASM_ASSERT(eq) -#endif - dc ivac, x6 mov x30, x10 1: ret |