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| author | danh-arm <dan.handley@arm.com> | 2016-07-15 18:55:43 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-07-15 18:55:43 +0100 |
| commit | aadb1350eed3c18aec6cd999519cef55d93678b3 (patch) | |
| tree | d851cbd6afa9f9b14676cde93bbf4e49f0cfebf1 /plat/arm/common/tsp/arm_tsp_setup.c | |
| parent | 9306f135922bc7811dfc1e24a755c38ce2e671cd (diff) | |
| parent | 91fad6551ee3e5529f9b442cd4a084251cdebe1d (diff) | |
Merge pull request #662 from sandrine-bailleux-arm/sb/rodata-xn
Map read-only data as execute-never
Diffstat (limited to 'plat/arm/common/tsp/arm_tsp_setup.c')
| -rw-r--r-- | plat/arm/common/tsp/arm_tsp_setup.c | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index 2a67fd10..09029f4c 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,16 +35,6 @@ #include <platform_tsp.h> #include <plat_arm.h> - -/* - * The next 3 constants identify the extents of the code & RO data region and - * the limit of the BL32 image. These addresses are used by the MMU setup code - * and therefore they must be page-aligned. It is the responsibility of the - * linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__ - * linker symbols refer to page-aligned addresses. - */ -#define BL32_RO_BASE (unsigned long)(&__RO_START__) -#define BL32_RO_LIMIT (unsigned long)(&__RO_END__) #define BL32_END (unsigned long)(&__BL32_END__) #if USE_COHERENT_MEM @@ -98,13 +88,16 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_configure_mmu_el1(BL32_RO_BASE, - (BL32_END - BL32_RO_BASE), - BL32_RO_BASE, - BL32_RO_LIMIT + arm_setup_page_tables(BL32_BASE, + (BL32_END - BL32_BASE), + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT #if USE_COHERENT_MEM , BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el1(0); } |