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| author | danh-arm <dan.handley@arm.com> | 2016-06-13 11:09:08 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-06-13 11:09:08 +0100 |
| commit | eae9d912503844e8ab8ac5851a638edd7fa7ac33 (patch) | |
| tree | a299531858aaeca14755a5b86fd2b9ff7fa232f8 /plat | |
| parent | b6b671c4ac4bd5595306863225bb3bece1e6135c (diff) | |
| parent | 68b105ae4794fa4f37392d17a0c898478d2f2a8f (diff) | |
Merge pull request #646 from davwan01/dw/gicv3-wakeup
CSS: Add support to wake up the core from wfi in GICv3
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/css/common/css_pm.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index b6f94ac2..801d9375 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -262,8 +262,14 @@ void css_cpu_standby(plat_local_state_t cpu_state) assert(cpu_state == ARM_LOCAL_STATE_RET); scr = read_scr_el3(); - /* Enable PhysicalIRQ bit for NS world to wake the CPU */ - write_scr_el3(scr | SCR_IRQ_BIT); + /* + * Enable the Non secure interrupt to wake the CPU. + * In GICv3 affinity routing mode, the non secure group1 interrupts use + * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. + * Enabling both the bits works for both GICv2 mode and GICv3 affinity + * routing mode. + */ + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); isb(); dsb(); wfi(); |