diff options
| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-20 21:43:27 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 08:49:36 +0100 |
| commit | 399fb08fff2e4a0cad4cd1cf0ece84db6670447f (patch) | |
| tree | 870a276f6e367046f563809a9e9e186e958b640c /services/spd/tspd/tspd_pm.c | |
| parent | 239b04fa31647100c537852b4a3fc8bd47e33aa6 (diff) | |
Use a vector table for TSP entrypoints
The TSP has a number of entrypoints used by the TSP on different
occasions. These were provided to the TSPD as a table of function
pointers, and required the TSPD to read the entry in the table,
which is in TSP memory, in order to program the exception return
address.
Ideally, the TSPD has no access to the TSP memory.
This patch changes the table of function pointers into a vector
table of single instruction entrypoints. This allows the TSPD to
calculate the entrypoint address instead of read it.
Fixes ARM-software/tf-issues#160
Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
Diffstat (limited to 'services/spd/tspd/tspd_pm.c')
| -rw-r--r-- | services/spd/tspd/tspd_pm.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c index d99aa222..2f204494 100644 --- a/services/spd/tspd/tspd_pm.c +++ b/services/spd/tspd/tspd_pm.c @@ -55,11 +55,11 @@ static int32_t tspd_cpu_off_handler(uint64_t cookie) uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; - assert(tsp_entry_info); + assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); /* Program the entry point and enter the TSP */ - cm_set_elr_el3(SECURE, (uint64_t) tsp_entry_info->cpu_off_entry); + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); rc = tspd_synchronous_sp_entry(tsp_ctx); /* @@ -89,14 +89,14 @@ static void tspd_cpu_suspend_handler(uint64_t power_state) uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; - assert(tsp_entry_info); + assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); /* Program the entry point, power_state parameter and enter the TSP */ write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), CTX_GPREG_X0, power_state); - cm_set_elr_el3(SECURE, (uint64_t) tsp_entry_info->cpu_suspend_entry); + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); rc = tspd_synchronous_sp_entry(tsp_ctx); /* @@ -123,11 +123,11 @@ static void tspd_cpu_on_finish_handler(uint64_t cookie) uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; - assert(tsp_entry_info); + assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); /* Initialise this cpu's secure context */ - tspd_init_secure_context((uint64_t) tsp_entry_info->cpu_on_entry, + tspd_init_secure_context((uint64_t) &tsp_vectors->cpu_on_entry, TSP_AARCH64, mpidr, tsp_ctx); @@ -158,14 +158,14 @@ static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level) uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; - assert(tsp_entry_info); + assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); /* Program the entry point, suspend_level and enter the SP */ write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), CTX_GPREG_X0, suspend_level); - cm_set_elr_el3(SECURE, (uint64_t) tsp_entry_info->cpu_resume_entry); + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); rc = tspd_synchronous_sp_entry(tsp_ctx); /* |