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authorAchin Gupta <achin.gupta@arm.com>2014-07-31 11:19:11 +0100
committerSoby Mathew <soby.mathew@arm.com>2014-08-19 14:29:23 +0100
commit0a46e2c3408ed719294de834177363d9adfeca06 (patch)
tree6052dce8441b1076ca9845017ee7e1b13ab96eea /services/std_svc/psci/psci_helpers.S
parent84c9f1003c911432a4036d03c5394894cb5757d2 (diff)
Add APIs to preserve highest affinity level in OFF state
This patch adds APIs to find, save and retrieve the highest affinity level which will enter or exit from the physical OFF state during a PSCI power management operation. The level is stored in per-cpu data. It then reworks the PSCI implementation to perform cache maintenance only when the handler for the highest affinity level to enter/exit the OFF state is called. For example. during a CPU_SUSPEND operation, state management is done prior to calling the affinity level specific handlers. The highest affinity level which will be turned off is determined using the psci_find_max_phys_off_afflvl() API. This level is saved using the psci_set_max_phys_off_afflvl() API. In the code that does generic handling for each level, prior to performing cache maintenance it is first determined if the current affinity level matches the value returned by psci_get_max_phys_off_afflvl(). Cache maintenance is done if the values match. This change allows the last CPU in a cluster to perform cache maintenance independently. Earlier, cache maintenance was started in the level 0 handler and finished in the level 1 handler. This change in approach will facilitate implementation of tf-issues#98. Change-Id: I57233f0a27b3ddd6ddca6deb6a88b234525b0ae6
Diffstat (limited to 'services/std_svc/psci/psci_helpers.S')
-rw-r--r--services/std_svc/psci/psci_helpers.S28
1 files changed, 22 insertions, 6 deletions
diff --git a/services/std_svc/psci/psci_helpers.S b/services/std_svc/psci/psci_helpers.S
index 21b5688c..91c31725 100644
--- a/services/std_svc/psci/psci_helpers.S
+++ b/services/std_svc/psci/psci_helpers.S
@@ -30,7 +30,9 @@
#include <arch.h>
#include <asm_macros.S>
+#include <assert_macros.S>
#include <platform_def.h>
+#include <psci.h>
.globl psci_do_pwrdown_cache_maintenance
.globl psci_do_pwrup_cache_maintenance
@@ -38,18 +40,31 @@
/* -----------------------------------------------------------------------
* void psci_do_pwrdown_cache_maintenance(uint32_t affinity level);
*
- * This function performs cache maintenance before this cpu is powered
- * off. The levels of cache affected are determined by the affinity level
- * which is passed as the argument. Additionally, this function also
- * ensures that stack memory is correctly flushed out to avoid coherency
- * issues due to a change in its memory attributes after the data cache
- * is disabled.
+ * This function performs cache maintenance if the specified affinity
+ * level is the equal to the level of the highest affinity instance which
+ * will be/is physically powered off. The levels of cache affected are
+ * determined by the affinity level which is passed as the argument i.e.
+ * level 0 results in a flush of the L1 cache. Both the L1 and L2 caches
+ * are flushed for a higher affinity level.
+ *
+ * Additionally, this function also ensures that stack memory is correctly
+ * flushed out to avoid coherency issues due to a change in its memory
+ * attributes after the data cache is disabled.
* -----------------------------------------------------------------------
*/
func psci_do_pwrdown_cache_maintenance
stp x29, x30, [sp,#-16]!
stp x19, x20, [sp,#-16]!
+ mov x19, x0
+ bl psci_get_max_phys_off_afflvl
+#if ASM_ASSERTION
+ cmp x0, #PSCI_INVALID_DATA
+ ASM_ASSERT(ne)
+#endif
+ cmp x0, x19
+ b.ne 1f
+
/* ---------------------------------------------
* Disable the Data Cache.
* ---------------------------------------------
@@ -127,6 +142,7 @@ do_stack_maintenance:
sub x1, sp, x0
bl inv_dcache_range
+1:
ldp x19, x20, [sp], #16
ldp x29, x30, [sp], #16
ret