diff options
| -rw-r--r-- | docs/cpu-specific-build-macros.md | 3 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 2 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 35 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
4 files changed, 48 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index 408af36b..5d34409f 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -63,6 +63,9 @@ For Cortex-A57, following errata build flags are defined : * `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. +* `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + 3. CPU Specific optimizations ------------------------------ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 7711e690..68d0821c 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -65,6 +65,8 @@ #define CPUACTLR_DIS_OVERREAD (1 << 52) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_DIS_STREAMING (3 << 27) +#define CPUACTLR_DIS_L1_STREAMING (3 << 25) /******************************************************************************* * L2 Control register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index d992f98b..ec32ce78 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -193,6 +193,37 @@ apply_826974: ret endfunc errata_a57_826974_wa + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #828024. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_828024_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_828024 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_828024: + mrs x1, CPUACTLR_EL1 + /* + * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 + * instructions here because the resulting bitmask doesn't fit in a + * 16-bit value so it cannot be encoded in a single instruction. + */ + orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_828024_wa /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. @@ -232,6 +263,10 @@ func cortex_a57_reset_func bl errata_a57_826974_wa #endif +#if ERRATA_A57_828024 + mov x0, x15 + bl errata_a57_828024_wa +#endif /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 3ea462bb..7d9f2b72 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -78,6 +78,10 @@ ERRATA_A57_813420 ?=0 # only to revision <= r1p1 of the Cortex A57 cpu. ERRATA_A57_826974 ?=0 +# Flag to apply erratum 828024 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_828024 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -97,3 +101,7 @@ $(eval $(call add_define,ERRATA_A57_813420)) # Process ERRATA_A57_826974 flag $(eval $(call assert_boolean,ERRATA_A57_826974)) $(eval $(call add_define,ERRATA_A57_826974)) + +# Process ERRATA_A57_828024 flag +$(eval $(call assert_boolean,ERRATA_A57_828024)) +$(eval $(call add_define,ERRATA_A57_828024)) |