diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/interrupt-framework-design.md | 20 | ||||
| -rw-r--r-- | docs/user-guide.md | 11 |
2 files changed, 17 insertions, 14 deletions
diff --git a/docs/interrupt-framework-design.md b/docs/interrupt-framework-design.md index 53707ae9..271cd921 100644 --- a/docs/interrupt-framework-design.md +++ b/docs/interrupt-framework-design.md @@ -399,12 +399,12 @@ requirements mentioned earlier. 1. It passes control to the Test Secure Payload to perform its initialisation. The TSP provides the address of the vector table `tsp_vectors` in the SP which also includes the handler for Secure-EL1 - interrupts in the `fiq_entry` field. The TSPD passes control to the TSP at + interrupts in the `sel1_intr_entry` field. The TSPD passes control to the TSP at this address when it receives a Secure-EL1 interrupt. The handover agreement between the TSP and the TSPD requires that the TSPD masks all interrupts (`PSTATE.DAIF` bits) when it calls - `tsp_fiq_entry()`. The TSP has to preserve the callee saved general + `tsp_sel1_intr_entry()`. The TSP has to preserve the callee saved general purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use `x0-x18` to enable its C runtime. @@ -514,7 +514,7 @@ runtime firmware is not aware of through its platform port. The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is described in Section 2.2.2. It is known to the TSPD service at build time. -The TSP implements an entrypoint (`tsp_fiq_entry()`) for handling Secure-EL1 +The TSP implements an entrypoint (`tsp_sel1_intr_entry()`) for handling Secure-EL1 interrupts taken in non-secure state and routed through the TSPD service (synchronous handling model). It passes the reference to this entrypoint via `tsp_vectors` to the TSPD service. @@ -700,9 +700,9 @@ takes the following actions upon being invoked. 3. It saves the system register context for the non-secure state by calling `cm_el1_sysregs_context_save(NON_SECURE);`. -4. It sets the `ELR_EL3` system register to `tsp_fiq_entry` and sets the +4. It sets the `ELR_EL3` system register to `tsp_sel1_intr_entry` and sets the `SPSR_EL3.DAIF` bits in the secure CPU context. It sets `x0` to - `TSP_HANDLE_FIQ_AND_RETURN`. If the TSP was in the middle of handling a + `TSP_HANDLE_SEL1_INTR_AND_RETURN`. If the TSP was in the middle of handling a standard SMC, then the `ELR_EL3` and `SPSR_EL3` registers in the secure CPU context are saved first. @@ -723,20 +723,20 @@ state.  -The TSP issues an SMC with `TSP_HANDLED_S_EL1_FIQ` as the function identifier to +The TSP issues an SMC with `TSP_HANDLED_S_EL1_INTR` as the function identifier to signal completion of interrupt handling. The TSP issues an SMC with `TSP_PREEMPTED` as the function identifier to signal generation of a non-secure interrupt in Secure-EL1. The TSPD service takes the following actions in `tspd_smc_handler()` function -upon receiving an SMC with `TSP_HANDLED_S_EL1_FIQ` and `TSP_PREEMPTED` as the +upon receiving an SMC with `TSP_HANDLED_S_EL1_INTR` and `TSP_PREEMPTED` as the function identifiers: 1. It ensures that the call originated from the secure state otherwise execution returns to the non-secure state with `SMC_UNK` in `x0`. -2. If the function identifier is `TSP_HANDLED_S_EL1_FIQ`, it restores the +2. If the function identifier is `TSP_HANDLED_S_EL1_INTR`, it restores the saved `ELR_EL3` and `SPSR_EL3` system registers back to the secure CPU context (see step 4 above) in case the TSP had been preempted by a non secure interrupt earlier. It does not save the secure context since the @@ -811,7 +811,7 @@ state. ##### 2.3.3.1 Test secure payload behavior The TSPD hands control of a Secure-EL1 interrupt to the TSP at the -`tsp_fiq_entry()`. The TSP handles the interrupt while ensuring that the +`tsp_sel1_intr_entry()`. The TSP handles the interrupt while ensuring that the handover agreement described in Section 2.2.2.1 is maintained. It updates some statistics by calling `tsp_update_sync_fiq_stats()`. It then calls `tsp_fiq_handler()` which. @@ -827,7 +827,7 @@ statistics by calling `tsp_update_sync_fiq_stats()`. It then calls end of interrupt processing. The TSP passes control back to the TSPD by issuing an SMC64 with -`TSP_HANDLED_S_EL1_FIQ` as the function identifier. +`TSP_HANDLED_S_EL1_INTR` as the function identifier. The TSP handles interrupts under the asynchronous model as follows. diff --git a/docs/user-guide.md b/docs/user-guide.md index bcdc645d..716ed7d8 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -278,10 +278,13 @@ performed. (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1. -* `TSPD_ROUTE_IRQ_TO_EL3`: A non zero value enables the routing model - for non-secure interrupts in which they are routed to EL3 (TSPD). The - default model (when the value is 0) is to route non-secure interrupts - to S-EL1 (TSP). +* `TSP_NS_INTR_ASYNC_PREEMPT`: A non zero value enables the interrupt + routing model which routes non-secure interrupts asynchronously from TSP + to EL3 causing immediate preemption of TSP. The EL3 is responsible + for saving and restoring the TSP context in this routing model. The + default routing model (when the value is 0) is to route non-secure + interrupts to TSP allowing it to save its context and hand over + synchronously to EL3 via an SMC. * `TRUSTED_BOARD_BOOT`: Boolean flag to include support for the Trusted Board Boot feature. When set to '1', BL1 and BL2 images include support to load |