diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/firmware-design.md | 19 | ||||
| -rw-r--r-- | docs/porting-guide.md | 6 |
2 files changed, 12 insertions, 13 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 11d6f1d0..1f799b64 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -151,19 +151,16 @@ BL1 performs minimal architectural initialization as follows. and Advanced SIMD execution are configured to not trap to EL3 by clearing the `CPTR_EL3.TFP` bit. - - `CNTFRQ_EL0`. The `CNTFRQ_EL0` register is programmed with the base - frequency of the system counter, which is retrieved from the first entry - in the frequency modes table. - - - Generic Timer. The system level implementation of the generic timer is - enabled through the memory mapped interface. - #### Platform initialization -BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from -the CCI-400 slave interface corresponding to the cluster that includes the -primary CPU. BL1 also initializes UART0 (PL011 console), which enables access to -the `printf` family of functions. +BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests +from the CCI-400 slave interface corresponding to the cluster that includes +the primary CPU. BL1 also initializes UART0 (PL011 console), which enables +access to the `printf` family of functions. The `CNTFRQ_EL0` register is +programmed with the base frequency of the system counter, which is retrieved +from the first entry in the frequency modes table. The system level +implementation of the generic timer is enabled through the memory mapped +interface. #### BL2 image load and execution diff --git a/docs/porting-guide.md b/docs/porting-guide.md index 56467fb9..6bba3604 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -446,8 +446,9 @@ This function executes with the MMU and data caches enabled. It is responsible for performing any remaining platform-specific setup that can occur after the MMU and data cache have been enabled. -In the ARM FVP port, it zeros out the ZI section and enables the system level -implementation of the generic timer counter. +In the ARM FVP port, this function enables system-level implementation of the +generic timer counter. It also initializes counter frequency for CPU's generic +timers. This function is also responsible for initializing the storage abstraction layer which is used to load further bootloader images. @@ -771,6 +772,7 @@ BL3-1 runtime services and normal world software can function correctly. The ARM FVP port does the following: * Initializes the generic interrupt controller. * Configures the CLCD controller. +* Initializes counter frequency for CPU's generic timer * Grants access to the system counter timer module * Initializes the FVP power controller device * Detects the system topology. |