diff options
Diffstat (limited to 'include/plat/arm/css')
| -rw-r--r-- | include/plat/arm/css/common/aarch64/css_macros.S | 4 | ||||
| -rw-r--r-- | include/plat/arm/css/common/css_def.h | 10 |
2 files changed, 12 insertions, 2 deletions
diff --git a/include/plat/arm/css/common/aarch64/css_macros.S b/include/plat/arm/css/common/aarch64/css_macros.S index 2a26eb70..9f18e09c 100644 --- a/include/plat/arm/css/common/aarch64/css_macros.S +++ b/include/plat/arm/css/common/aarch64/css_macros.S @@ -41,8 +41,8 @@ * --------------------------------------------- */ .macro plat_print_gic_regs - mov_imm x16, PLAT_CSS_GICD_BASE - mov_imm x17, PLAT_CSS_GICC_BASE + mov_imm x16, PLAT_ARM_GICD_BASE + mov_imm x17, PLAT_ARM_GICC_BASE arm_print_gic_regs .endm diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 98b69cb3..99491f88 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -61,6 +61,16 @@ #define CSS_IRQ_SEC_SYS_TIMER 91 /* + * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a + * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. + */ +#define CSS_G1S_IRQS CSS_IRQ_MHU, \ + CSS_IRQ_GPU_SMMU_0, \ + CSS_IRQ_TZC, \ + CSS_IRQ_TZ_WDOG, \ + CSS_IRQ_SEC_SYS_TIMER + +/* * SCP <=> AP boot configuration * * The SCP/AP boot configuration is a 32-bit word located at a known offset from |