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-rw-r--r--include/common/bl_common.h10
-rw-r--r--include/common/el3_common_macros.S2
-rw-r--r--include/common/firmware_image_package.h20
-rw-r--r--include/common/tbbr/tbbr_img_def.h22
-rw-r--r--include/lib/cpus/aarch64/cpu_macros.S2
-rw-r--r--include/plat/arm/board/common/board_arm_oid.h36
-rw-r--r--include/plat/arm/common/aarch64/arm_macros.S4
-rw-r--r--include/plat/arm/common/arm_def.h12
-rw-r--r--include/plat/arm/common/plat_arm.h4
-rw-r--r--include/plat/arm/css/common/aarch64/css_macros.S2
-rw-r--r--include/plat/arm/css/common/css_def.h10
-rw-r--r--include/plat/common/common_def.h2
-rw-r--r--include/plat/common/platform.h36
13 files changed, 81 insertions, 81 deletions
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index b7cb95aa..0ec7a8d8 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -245,14 +245,14 @@ typedef struct image_desc {
* This structure represents the superset of information that can be passed to
* BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
* populated only if BL2 detects its presence. A pointer to a structure of this
- * type should be passed in X0 to BL3-1's cold boot entrypoint.
+ * type should be passed in X0 to BL31's cold boot entrypoint.
*
- * Use of this structure and the X0 parameter is not mandatory: the BL3-1
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
* platform code can use other mechanisms to provide the necessary information
- * about BL3-2 and BL3-3 to the common and SPD code.
+ * about BL32 and BL33 to the common and SPD code.
*
- * BL3-1 image information is mandatory if this structure is used. If either of
- * the optional BL3-2 and BL3-3 image information is not provided, this is
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
* indicated by the respective image_info pointers being zero.
******************************************************************************/
typedef struct bl31_params {
diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S
index 0514e2a2..6f7136f9 100644
--- a/include/common/el3_common_macros.S
+++ b/include/common/el3_common_macros.S
@@ -104,7 +104,7 @@
/* -----------------------------------------------------------------------------
* This is the super set of actions that need to be performed during a cold boot
- * or a warm boot in EL3. This code is shared by BL1 and BL3-1.
+ * or a warm boot in EL3. This code is shared by BL1 and BL31.
*
* This macro will always perform reset handling, architectural initialisations
* and stack setup. The rest of the actions are optional because they might not
diff --git a/include/common/firmware_image_package.h b/include/common/firmware_image_package.h
index daa043a8..b9723957 100644
--- a/include/common/firmware_image_package.h
+++ b/include/common/firmware_image_package.h
@@ -49,7 +49,7 @@
{0xb28a4071, 0xd618, 0x4c87, 0x8b, 0x2e, {0xc6, 0xdc, 0xcd, 0x50, 0xf0, 0x96} }
#define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \
{0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} }
-#define UUID_SCP_FIRMWARE_BL30 \
+#define UUID_SCP_FIRMWARE_SCP_BL2 \
{0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} }
#define UUID_EL3_RUNTIME_FIRMWARE_BL31 \
{0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} }
@@ -64,24 +64,24 @@
{0x90e87e82, 0x60f8, 0x11e4, 0xa1, 0xb4, {0x77, 0x7a, 0x21, 0xb4, 0xf9, 0x4c} }
#define UUID_NON_TRUSTED_WORLD_KEY_CERT \
{0x3d87671c, 0x635f, 0x11e4, 0x97, 0x8d, {0x27, 0xc0, 0xc7, 0x14, 0x8a, 0xbd} }
-#define UUID_SCP_FIRMWARE_BL30_KEY_CERT \
+#define UUID_SCP_FW_KEY_CERT \
{0xa1214202, 0x60f8, 0x11e4, 0x8d, 0x9b, {0xf3, 0x3c, 0x0e, 0x15, 0xa0, 0x14} }
-#define UUID_EL3_RUNTIME_FIRMWARE_BL31_KEY_CERT \
+#define UUID_SOC_FW_KEY_CERT \
{0xccbeb88a, 0x60f9, 0x11e4, 0x9a, 0xd0, {0xeb, 0x48, 0x22, 0xd8, 0xdc, 0xf8} }
-#define UUID_SECURE_PAYLOAD_BL32_KEY_CERT \
+#define UUID_TRUSTED_OS_FW_KEY_CERT \
{0x03d67794, 0x60fb, 0x11e4, 0x85, 0xdd, {0xb7, 0x10, 0x5b, 0x8c, 0xee, 0x04} }
-#define UUID_NON_TRUSTED_FIRMWARE_BL33_KEY_CERT \
+#define UUID_NON_TRUSTED_FW_KEY_CERT \
{0x2a83d58a, 0x60fb, 0x11e4, 0x8a, 0xaf, {0xdf, 0x30, 0xbb, 0xc4, 0x98, 0x59} }
/* Content certificates */
-#define UUID_TRUSTED_BOOT_FIRMWARE_BL2_CERT \
+#define UUID_TRUSTED_BOOT_FW_CERT \
{0xea69e2d6, 0x635d, 0x11e4, 0x8d, 0x8c, {0x9f, 0xba, 0xbe, 0x99, 0x56, 0xa5} }
-#define UUID_SCP_FIRMWARE_BL30_CERT \
+#define UUID_SCP_FW_CONTENT_CERT \
{0x046fbe44, 0x635e, 0x11e4, 0xb2, 0x8b, {0x73, 0xd8, 0xea, 0xae, 0x96, 0x56} }
-#define UUID_EL3_RUNTIME_FIRMWARE_BL31_CERT \
+#define UUID_SOC_FW_CONTENT_CERT \
{0x200cb2e2, 0x635e, 0x11e4, 0x9c, 0xe8, {0xab, 0xcc, 0xf9, 0x2b, 0xb6, 0x66} }
-#define UUID_SECURE_PAYLOAD_BL32_CERT \
+#define UUID_TRUSTED_OS_FW_CONTENT_CERT \
{0x11449fa4, 0x635e, 0x11e4, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} }
-#define UUID_NON_TRUSTED_FIRMWARE_BL33_CERT \
+#define UUID_NON_TRUSTED_FW_CONTENT_CERT \
{0xf3c1c48e, 0x635d, 0x11e4, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} }
typedef struct fip_toc_header {
diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h
index fabe0b94..ad10e2e5 100644
--- a/include/common/tbbr/tbbr_img_def.h
+++ b/include/common/tbbr/tbbr_img_def.h
@@ -37,8 +37,8 @@
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_ID 1
-/* SCP Firmware BL3-0 */
-#define BL30_IMAGE_ID 2
+/* SCP Firmware SCP_BL2 */
+#define SCP_BL2_IMAGE_ID 2
/* EL3 Runtime Firmware BL31 */
#define BL31_IMAGE_ID 3
@@ -50,18 +50,18 @@
#define BL33_IMAGE_ID 5
/* Certificates */
-#define BL2_CERT_ID 6
+#define TRUSTED_BOOT_FW_CERT_ID 6
#define TRUSTED_KEY_CERT_ID 7
-#define BL30_KEY_CERT_ID 8
-#define BL31_KEY_CERT_ID 9
-#define BL32_KEY_CERT_ID 10
-#define BL33_KEY_CERT_ID 11
+#define SCP_FW_KEY_CERT_ID 8
+#define SOC_FW_KEY_CERT_ID 9
+#define TRUSTED_OS_FW_KEY_CERT_ID 10
+#define NON_TRUSTED_FW_KEY_CERT_ID 11
-#define BL30_CERT_ID 12
-#define BL31_CERT_ID 13
-#define BL32_CERT_ID 14
-#define BL33_CERT_ID 15
+#define SCP_FW_CONTENT_CERT_ID 12
+#define SOC_FW_CONTENT_CERT_ID 13
+#define TRUSTED_OS_FW_CONTENT_CERT_ID 14
+#define NON_TRUSTED_FW_CONTENT_CERT_ID 15
/* Non-Trusted ROM Firmware NS_BL1U */
#define NS_BL1U_IMAGE_ID 16
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 72c35fb6..f34f0783 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -46,7 +46,7 @@ CPU_MIDR: /* cpu_ops midr */
CPU_RESET_FUNC: /* cpu_ops reset_func */
.space 8
#endif
-#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */
+#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
.space 8
CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
diff --git a/include/plat/arm/board/common/board_arm_oid.h b/include/plat/arm/board/common/board_arm_oid.h
index b29212e4..cbf22900 100644
--- a/include/plat/arm/board/common/board_arm_oid.h
+++ b/include/plat/arm/board/common/board_arm_oid.h
@@ -44,9 +44,9 @@
/* TrustedFirmwareNVCounter - Non-volatile counter extension */
-#define TZ_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.1"
+#define TRUSTED_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.1"
/* NonTrustedFirmwareNVCounter - Non-volatile counter extension */
-#define NTZ_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.2"
+#define NON_TRUSTED_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.2"
/*
@@ -54,11 +54,11 @@
*/
/* APFirmwareUpdaterConfigHash - BL2U */
-#define BL2U_HASH_OID "1.3.6.1.4.1.4128.2100.101"
+#define AP_FWU_CFG_HASH_OID "1.3.6.1.4.1.4128.2100.101"
/* SCPFirmwareUpdaterConfigHash - SCP_BL2U */
-#define SCP_BL2U_HASH_OID "1.3.6.1.4.1.4128.2100.102"
+#define SCP_FWU_CFG_HASH_OID "1.3.6.1.4.1.4128.2100.102"
/* FirmwareUpdaterHash - NS_BL2U */
-#define NS_BL2U_HASH_OID "1.3.6.1.4.1.4128.2100.103"
+#define FWU_HASH_OID "1.3.6.1.4.1.4128.2100.103"
/* TrustedWatchdogRefreshTime */
#define TRUSTED_WATCHDOG_TIME_OID "1.3.6.1.4.1.4128.2100.104"
@@ -68,7 +68,7 @@
*/
/* TrustedBootFirmwareHash - BL2 */
-#define BL2_HASH_OID "1.3.6.1.4.1.4128.2100.201"
+#define TRUSTED_BOOT_FW_HASH_OID "1.3.6.1.4.1.4128.2100.201"
/*
@@ -78,9 +78,9 @@
/* PrimaryDebugCertificatePK */
#define PRIMARY_DEBUG_PK_OID "1.3.6.1.4.1.4128.2100.301"
/* TrustedWorldPK */
-#define TZ_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.302"
+#define TRUSTED_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.302"
/* NonTrustedWorldPK */
-#define NTZ_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.303"
+#define NON_TRUSTED_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.303"
/*
@@ -100,7 +100,7 @@
*/
/* SoCFirmwareContentCertPK */
-#define BL31_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.501"
+#define SOC_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.501"
/*
@@ -112,7 +112,7 @@
/* SoCConfigHash */
#define SOC_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.602"
/* SoCAPFirmwareHash - BL31 */
-#define BL31_HASH_OID "1.3.6.1.4.1.4128.2100.603"
+#define SOC_AP_FW_HASH_OID "1.3.6.1.4.1.4128.2100.603"
/*
@@ -120,16 +120,16 @@
*/
/* SCPFirmwareContentCertPK */
-#define BL30_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.701"
+#define SCP_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.701"
/*
* SCP Firmware Content Certificate
*/
-/* SCPFirmwareHash - BL30 */
-#define BL30_HASH_OID "1.3.6.1.4.1.4128.2100.801"
-/* SCPRomPatchHash - BL0_PATCH */
+/* SCPFirmwareHash - SCP_BL2 */
+#define SCP_FW_HASH_OID "1.3.6.1.4.1.4128.2100.801"
+/* SCPRomPatchHash - SCP_BL1_PATCH */
#define SCP_ROM_PATCH_HASH_OID "1.3.6.1.4.1.4128.2100.802"
@@ -138,7 +138,7 @@
*/
/* TrustedOSFirmwareContentCertPK */
-#define BL32_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.901"
+#define TRUSTED_OS_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.901"
/*
@@ -146,7 +146,7 @@
*/
/* TrustedOSFirmwareHash - BL32 */
-#define BL32_HASH_OID "1.3.6.1.4.1.4128.2100.1001"
+#define TRUSTED_OS_FW_HASH_OID "1.3.6.1.4.1.4128.2100.1001"
/*
@@ -154,7 +154,7 @@
*/
/* NonTrustedFirmwareContentCertPK */
-#define BL33_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.1101"
+#define NON_TRUSTED_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.1101"
/*
@@ -162,6 +162,6 @@
*/
/* NonTrustedWorldBootloaderHash - BL33 */
-#define BL33_HASH_OID "1.3.6.1.4.1.4128.2100.1201"
+#define NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID "1.3.6.1.4.1.4128.2100.1201"
#endif /* __BOARD_ARM_OID_H__ */
diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S
index eaaa62fe..384bb514 100644
--- a/include/plat/arm/common/aarch64/arm_macros.S
+++ b/include/plat/arm/common/aarch64/arm_macros.S
@@ -57,7 +57,7 @@ spacer:
/* ---------------------------------------------
* The below utility macro prints out relevant GIC
* registers whenever an unhandled exception is
- * taken in BL3-1 on ARM standard platforms.
+ * taken in BL31 on ARM standard platforms.
* Expects: GICD base in x16, GICC base in x17
* Clobbers: x0 - x10, sp
* ---------------------------------------------
@@ -125,7 +125,7 @@ cci_iface_regs:
/* ------------------------------------------------
* The below required platform porting macro prints
* out relevant interconnect registers whenever an
- * unhandled exception is taken in BL3-1.
+ * unhandled exception is taken in BL31.
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 4a50c1c8..b2db6160 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -41,7 +41,7 @@
* Definitions common to all ARM standard platforms
*****************************************************************************/
-/* Special value used to verify platform parameters from BL2 to BL3-1 */
+/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define ARM_CLUSTER_COUNT 2
@@ -257,7 +257,7 @@
* BL2 specific defines.
******************************************************************************/
/*
- * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#if TRUSTED_BOARD_BOOT
@@ -268,11 +268,11 @@
#define BL2_LIMIT BL31_BASE
/*******************************************************************************
- * BL3-1 specific defines.
+ * BL31 specific defines.
******************************************************************************/
/*
- * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth.
+ * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
+ * current BL31 debug size plus a little space for growth.
*/
#define BL31_BASE (ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE - \
@@ -281,7 +281,7 @@
#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/*******************************************************************************
- * BL3-2 specific defines.
+ * BL32 specific defines.
******************************************************************************/
/*
* On ARM standard platforms, the TSP can execute from Trusted SRAM,
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 32c062d1..3b6a04ba 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -87,7 +87,7 @@ void arm_configure_mmu_el3(unsigned long total_base,
#else
/*
- * Empty macros for all other BL stages other than BL3-1
+ * Empty macros for all other BL stages other than BL31
*/
#define ARM_INSTANTIATE_LOCK
#define arm_lock_init()
@@ -171,7 +171,7 @@ void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
void arm_bl2u_platform_setup(void);
void arm_bl2u_plat_arch_setup(void);
-/* BL3-1 utility functions */
+/* BL31 utility functions */
void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2);
void arm_bl31_platform_setup(void);
diff --git a/include/plat/arm/css/common/aarch64/css_macros.S b/include/plat/arm/css/common/aarch64/css_macros.S
index 9f18e09c..9124fdc7 100644
--- a/include/plat/arm/css/common/aarch64/css_macros.S
+++ b/include/plat/arm/css/common/aarch64/css_macros.S
@@ -36,7 +36,7 @@
/* ---------------------------------------------
* The below required platform porting macro
* prints out relevant GIC registers whenever an
- * unhandled exception is taken in BL3-1.
+ * unhandled exception is taken in BL31.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 3fa4c153..c900278b 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -82,7 +82,7 @@
* primary, according to the shift and mask definitions below.
*
* Note that the value stored at this address is only valid at boot time, before
- * the BL3-0 image is transferred to SCP.
+ * the SCP_BL2 image is transferred to SCP.
*/
#define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80)
#define PRIMARY_CPU_SHIFT 8
@@ -110,11 +110,11 @@
************************************************************************/
/*
- * Load address of BL3-0 in CSS platform ports
- * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
- * SCP, it is discarded and BL3-1 is loaded over the top.
+ * Load address of SCP_BL2 in CSS platform ports
+ * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the
+ * SCP, it is discarded and BL31 is loaded over the top.
*/
-#define BL30_BASE BL31_BASE
+#define SCP_BL2_BASE BL31_BASE
#define SCP_BL2U_BASE BL31_BASE
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index 4175b145..744c22eb 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -55,7 +55,7 @@
* avoid subtle integer overflow errors due to implicit integer type promotion
* when working with 32-bit values.
*
- * The TSP linker script includes some of these definitions to define the BL3-2
+ * The TSP linker script includes some of these definitions to define the BL32
* memory map, but the GNU LD does not support the 'ull' suffix, causing the
* build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
* will add the 'ull' suffix only when the macro __LINKER__ is not defined
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index b3213b8f..c21f9ee8 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -134,7 +134,7 @@ struct meminfo *bl2_plat_sec_mem_layout(void);
/*
* This function returns a pointer to the shared memory that the platform has
- * kept aside to pass trusted firmware related information that BL3-1
+ * kept aside to pass trusted firmware related information that BL31
* could need
*/
struct bl31_params *bl2_plat_get_bl31_params(void);
@@ -147,14 +147,14 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void);
/*
* This function flushes to main memory all the params that are
- * passed to BL3-1
+ * passed to BL31
*/
void bl2_plat_flush_bl31_params(void);
/*
* The next 2 functions allow the platform to change the entrypoint information
- * for the mandatory 3rd level BL images, BL3-1 and BL3-3. This is done after
- * BL2 has loaded those images into memory but before BL3-1 is executed.
+ * for the mandatory 3rd level BL images, BL31 and BL33. This is done after
+ * BL2 has loaded those images into memory but before BL31 is executed.
*/
void bl2_plat_set_bl31_ep_info(struct image_info *image,
struct entry_point_info *ep);
@@ -162,30 +162,30 @@ void bl2_plat_set_bl31_ep_info(struct image_info *image,
void bl2_plat_set_bl33_ep_info(struct image_info *image,
struct entry_point_info *ep);
-/* Gets the memory layout for BL3-3 */
+/* Gets the memory layout for BL33 */
void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
/*******************************************************************************
- * Conditionally mandatory BL2 functions: must be implemented if BL3-0 image
+ * Conditionally mandatory BL2 functions: must be implemented if SCP_BL2 image
* is supported
******************************************************************************/
-/* Gets the memory layout for BL3-0 */
-void bl2_plat_get_bl30_meminfo(struct meminfo *mem_info);
+/* Gets the memory layout for SCP_BL2 */
+void bl2_plat_get_scp_bl2_meminfo(struct meminfo *mem_info);
/*
- * This function is called after loading BL3-0 image and it is used to perform
+ * This function is called after loading SCP_BL2 image and it is used to perform
* any platform-specific actions required to handle the SCP firmware.
*/
-int bl2_plat_handle_bl30(struct image_info *bl30_image_info);
+int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info);
/*******************************************************************************
- * Conditionally mandatory BL2 functions: must be implemented if BL3-2 image
+ * Conditionally mandatory BL2 functions: must be implemented if BL32 image
* is supported
******************************************************************************/
void bl2_plat_set_bl32_ep_info(struct image_info *image,
struct entry_point_info *ep);
-/* Gets the memory layout for BL3-2 */
+/* Gets the memory layout for BL32 */
void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
/*******************************************************************************
@@ -210,7 +210,7 @@ void bl2u_platform_setup(void);
int bl2u_plat_handle_scp_bl2u(void);
/*******************************************************************************
- * Mandatory BL3-1 functions
+ * Mandatory BL31 functions
******************************************************************************/
void bl31_early_platform_setup(struct bl31_params *from_bl2,
void *plat_params_from_bl2);
@@ -220,26 +220,26 @@ void bl31_plat_runtime_setup(void);
struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type);
/*******************************************************************************
- * Mandatory PSCI functions (BL3-1)
+ * Mandatory PSCI functions (BL31)
******************************************************************************/
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const struct plat_psci_ops **);
const unsigned char *plat_get_power_domain_tree_desc(void);
/*******************************************************************************
- * Optional PSCI functions (BL3-1).
+ * Optional PSCI functions (BL31).
******************************************************************************/
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states,
unsigned int ncpu);
/*******************************************************************************
- * Optional BL3-1 functions (may be overridden)
+ * Optional BL31 functions (may be overridden)
******************************************************************************/
void bl31_plat_enable_mmu(uint32_t flags);
/*******************************************************************************
- * Optional BL3-2 functions (may be overridden)
+ * Optional BL32 functions (may be overridden)
******************************************************************************/
void bl32_plat_enable_mmu(uint32_t flags);
@@ -261,7 +261,7 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
unsigned int platform_get_core_pos(unsigned long mpidr);
/*******************************************************************************
- * Mandatory PSCI Compatibility functions (BL3-1)
+ * Mandatory PSCI Compatibility functions (BL31)
******************************************************************************/
int platform_setup_pm(const plat_pm_ops_t **);
generated by cgit (git 2.34.1) at 2025-07-16 15:10:13 +0000