diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 7 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 24 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 4 |
3 files changed, 31 insertions, 4 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index ec184641..306b42e7 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -29,6 +29,7 @@ */ #include <arch.h> #include <asm_macros.S> +#include <bl_common.h> #include <cortex_a53.h> #include <cpu_macros.S> #include <plat_macros.S> @@ -58,13 +59,17 @@ func cortex_a53_disable_smp func cortex_a53_reset_func /* --------------------------------------------- - * As a bare minimum enable the SMP bit. + * As a bare minimum enable the SMP bit if it is + * not already set. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 + tst x0, #CPUECTLR_SMP_BIT + b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb +skip_smp_setup: ret func cortex_a53_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index dab16d7e..3334e688 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -30,6 +30,7 @@ #include <arch.h> #include <asm_macros.S> #include <assert_macros.S> +#include <bl_common.h> #include <cortex_a57.h> #include <cpu_macros.S> #include <plat_macros.S> @@ -99,9 +100,17 @@ func errata_a57_806969_wa ret #endif apply_806969: + /* + * Test if errata has already been applied in an earlier + * invocation of the reset handler and does not need to + * be applied again. + */ mrs x1, CPUACTLR_EL1 + tst x1, #CPUACTLR_NO_ALLOC_WBWA + b.ne skip_806969 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA msr CPUACTLR_EL1, x1 +skip_806969: ret @@ -123,9 +132,17 @@ func errata_a57_813420_wa ret #endif apply_813420: + /* + * Test if errata has already been applied in an earlier + * invocation of the reset handler and does not need to + * be applied again. + */ mrs x1, CPUACTLR_EL1 + tst x1, #CPUACTLR_DCC_AS_DCCI + b.ne skip_813420 orr x1, x1, #CPUACTLR_DCC_AS_DCCI msr CPUACTLR_EL1, x1 +skip_813420: ret /* ------------------------------------------------- @@ -154,13 +171,18 @@ func cortex_a57_reset_func mov x0, x20 bl errata_a57_813420_wa #endif + /* --------------------------------------------- - * As a bare minimum enable the SMP bit. + * As a bare minimum enable the SMP bit if it is + * not already set. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 + tst x0, #CPUECTLR_SMP_BIT + b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 +skip_smp_setup: isb ret x19 diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 5680bce6..d829f60b 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -37,7 +37,7 @@ #endif /* Reset fn is needed in BL at reset vector */ -#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) +#if IMAGE_BL1 || IMAGE_BL31 /* * The reset handler common to all platforms. After a matching * cpu_ops structure entry is found, the correponding reset_handler @@ -64,7 +64,7 @@ func reset_handler 1: ret -#endif /* IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) */ +#endif /* IMAGE_BL1 || IMAGE_BL31 */ #if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ /* |