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path: root/docs/cpu-specific-build-macros.md
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2016-04-21Doc: Add links to the A53/A57 Errata Notice documentsSandrine Bailleux
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores Software Developers Errata Notice documents in the ARM CPU Specific Build Macros document. Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
2016-04-21Add support for Cortex-A57 erratum 833471 workaroundSandrine Bailleux
Change-Id: I86ac81ffd7cd094ce68c4cceb01c16563671a063
2016-04-21Add support for Cortex-A57 erratum 826977 workaroundSandrine Bailleux
Change-Id: Icaacd19c4cef9c10d02adcc2f84a4d7c97d4bcfa
2016-04-21Add support for Cortex-A57 erratum 829520 workaroundSandrine Bailleux
Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439
2016-04-21Add support for Cortex-A57 erratum 828024 workaroundSandrine Bailleux
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d
2016-04-21Add support for Cortex-A57 erratum 826974 workaroundSandrine Bailleux
Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4
2016-02-18Cortex-A57: Add link to software optimization guideSandrine Bailleux
This patch adds a link to the Cortex-A57 Software Optimization Guide in the ARM CPU Specific Build Macros document to justify the default value of the A57_DISABLE_NON_TEMPORAL_HINT build flag. Change-Id: I9779e42a4bb118442b2b64717ce143314ec9dd16
2016-02-08Disable non-temporal hint on Cortex-A53/57Sandrine Bailleux
The LDNP/STNP instructions as implemented on Cortex-A53 and Cortex-A57 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The ARMv8-A architecture (see Document ARM DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. This patch introduces 2 new build flags: A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT to enforce this behaviour on Cortex-A53 and Cortex-A57. They are enabled by default. The string printed in debug builds when a specific CPU errata workaround is compiled in but skipped at runtime has been generalised, so that it can be reused for the non-temporal hint use case as well. Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
2015-08-05cortex_a53: Add A53 errata #826319, #836870Jimmy Huang
- Apply a53 errata #826319 to revision <= r0p2 - Apply a53 errata #836870 to revision <= r0p3 - Update docs/cpu-specific-build-macros.md for newly added errata build flags Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
2015-02-02Miscellaneous doc fixes for v1.1Sandrine Bailleux
Change-Id: Iaf9d6305edc478d39cf1b37c8a70ccdf723e8ef9
2015-01-07Create Table of Content links in markdown filesJoakim Bech
Fixes arm-software/tf-issues#276
2014-10-29Optimize Cortex-A57 cluster power down sequence on JunoSoby Mathew
This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
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