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2014-08-27Miscellaneous documentation fixesSandrine Bailleux
This patch gathers miscellaneous minor fixes to the documentation, and comments in the source code. Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b Co-Authored-By: Soby Mathew <soby.mathew@arm.com> Co-Authored-By: Dan Handley <dan.handley@arm.com>
2014-08-27Add information about Juno in firmware-design.mdJuan Castillo
This patch reorganizes the firmware design guide to add information about the port of the ARM Trusted Firmware to the Juno ARM development platform. Change-Id: I0b80e2e7a35ccad1af2e971506cfb7fe505f8b84
2014-08-20Add documentation for CPU specific abstraction and Errata workaroundsSoby Mathew
This patch adds documentation for CPU specific abstraction in the firmware- design.md and adds a new document cpu-errata-workarounds.md to describe the cpu errata workaround build flags. Change-Id: Ia08c2fec0b868a0a107d0264e87a60182797a1bd
2014-08-14Merge pull request #184 from jcastillo-arm/jc/tf-issues/100danh-arm
FVP: make usage of Trusted DRAM optional at build time
2014-08-14FVP: make usage of Trusted DRAM optional at build timeJuan Castillo
This patch groups the current contents of the Trusted DRAM region at address 0x00_0600_0000 (entrypoint mailboxes and BL3-1 parameters) in a single shared memory area that may be allocated to Trusted SRAM (default) or Trusted DRAM at build time by setting the FVP_SHARED_DATA_LOCATION make variable. The size of this shared memory is 4096 bytes. The combination 'Shared data in Trusted SRAM + TSP in Trusted DRAM' is not currently supported due to restrictions in the maximum number of mmu tables that can be created. Documentation has been updated to reflect these changes. Fixes ARM-software/tf-issues#100 Change-Id: I26ff04d33ce4cacf8d770d1a1e24132b4fc53ff0
2014-08-11Add compilation macro for each BL stageSoby Mathew
This patch defines a compile time macro for each boot loader stage which allows compilation of code only for a specific stage. Change-Id: I3a4068404cd3dc26d652556ca9ca7afea8dd28ef
2014-08-01Support asynchronous method for BL3-2 initializationVikram Kanigiri
This patch adds support for BL3-2 initialization by asynchronous method where BL3-1 transfers control to BL3-2 using world switch. After BL3-2 initialization, it transfers control to BL3-3 via SPD service handler. The SPD service handler initializes the CPU context to BL3-3 entrypoint depending on the return function indentifier from TSP initialization. Fixes ARM-software/TF-issues#184 Change-Id: I7b135c2ceeb356d3bb5b6a287932e96ac67c7a34
2014-07-11Update the documentation about the memory layout on FVPSandrine Bailleux
Update the "Memory layout on FVP platforms" section in the Firmware Design document to reflect the overlaying of BL1 and BL2 images by BL3-1 and BL3-2. Also update the Porting Guide document to mention the BL31_PROGBITS_LIMIT and BL32_PROGBITS_LIMIT constants. Change-Id: I0b23dae5b5b4490a01be7ff7aa80567cff34bda8
2014-06-03Document design of the Interrupt Mangement FrameworkAchin Gupta
This patch adds documentation that describes the design of the Interrupt management framework in the ARM Trusted Firmware. The porting-guide.md has also been updated to describe the interface that should be implemented by each platform to support this framework. Change-Id: I3eda48e5c9456e6a9516956bee16a29e366633b7 Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
2014-06-03Merge pull request #119 from 'soby-mathew:sm/doc_crash_reporting'Dan Handley
2014-06-03Documentation for BL3-1 hardening and reset vectorVikram Kanigiri
Update documentation with BL3-1 hardening interface changes and for using BL3-1 as a reset vector feature Change-Id: Iafdd05e7a8e66503409f2acc934372efef5bc51b
2014-06-02Documentation for the new crash reporting implementationSoby Mathew
This patch modifies and adds to the existing documentation for the crash reporting implementation in BL3-1. Change-Id: I2cfbfeeeb64996ec7d19a9ddf95295482899b4bd
2014-05-23Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2Andrew Thoelke
2014-05-23doc: Update information about the memory layoutSandrine Bailleux
Rework the "Memory layout on FVP platforms" section in the Firmware Design document. Add information about where the TSP image fits in the memory layout when present. Add documentation for the base addresses of each bootloader image in the porting guide. Change-Id: I4afb2605e008a1cb28c44a697804f2cb6bb4c9aa
2014-05-19Improve BL3-0 documentationHarry Liebel
Provide some information about the expected use of BL3-0. Fixes ARM-software/tf-issues#144 Change-Id: I5c8d59a675578394be89481ae4ec39ca37522750
2014-04-24FVP secure memory support documentationHarry Liebel
Fixes ARM-software/tf-issues#64 Change-Id: I4e56c25f9dc7f486fbf6fa2f7d8253874119b989
2014-04-08Define frequency of system counter in platform codeSandrine Bailleux
BL3-1 architecture setup code programs the system counter frequency into the CNTFRQ_EL0 register. This frequency is defined by the platform, though. This patch introduces a new platform hook that the architecture setup code can call to retrieve this information. In the ARM FVP port, this returns the first entry of the frequency modes table from the memory mapped generic timer. All system counter setup code has been removed from BL1 as some platforms may not have initialized the system counters at this stage. The platform specific settings done exclusively in BL1 have been moved to BL3-1. In the ARM FVP port, this consists in enabling and initializing the System level generic timer. Also, the frequency change request in the counter control register has been set to 0 to make it explicit it's using the base frequency. The CNTCR_FCREQ() macro has been fixed in this context to give an entry number rather than a bitmask. In future, when support for firmware update is implemented, there is a case where BL1 platform specific code will need to program the counter frequency. This should be implemented at that time. This patch also updates the relevant documentation. It properly fixes ARM-software/tf-issues#24 Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
2014-04-08Revert "Move architecture timer setup to platform-specific code"Sandrine Bailleux
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5 because it introduced a bug: the CNTFRQ_EL0 register was no longer programmed by all CPUs. bl31_platform_setup() function is invoked only in the cold boot path and consequently only on the primary cpu. A subsequent commit will correctly implement the necessary changes to the counter frequency setup code. Fixes ARM-software/tf-issues#125 Conflicts: docs/firmware-design.md plat/fvp/bl31_plat_setup.c Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
2014-03-26Initialise UART console in all bootloader stagesVikram Kanigiri
This patch reworks the console driver to ensure that each bootloader stage initializes it independently. As a result, both BL3-1 and BL2 platform code now calls console_init() instead of relying on BL1 to perform console setup Fixes ARM-software/tf-issues#120 Change-Id: Ic4d66e0375e40a2fc7434afcabc8bbb4715c14ab
2014-03-10Move architecture timer setup to platform-specific codeJeenu Viswambharan
At present, bl1_arch_setup() and bl31_arch_setup() program the counter frequency using a value from the memory mapped generic timer. The generic timer however is not necessarily present on all ARM systems (although it is architected to be present on all server systems). This patch moves the timer setup to platform-specific code and updates the relevant documentation. Also, CNTR.FCREQ is set as the specification requires the bit corresponding to the counter's frequency to be set when enabling. Since we intend to use the base frequency, set bit 8. Fixes ARM-software/tf-issues#24 Change-Id: I32c52cf882253e01f49056f47c58c23e6f422652
2014-02-28Consolidate design and porting documentationDan Handley
Consolidate firmware-design.md and porting-guide.pm so that recently added sections fit better with pre-existing sections. Make the documentation more consistent in use of terminology. Change-Id: Id87050b096122fbd845189dc2fe1cd17c3003468
2014-02-28Add EL3 runtime services and SPD documentationDan Handley
1. Add design information on EL3 runtime services and Secure-EL1 Payload Dispatchers (SPD) to firmware-design.md. 2. Create new EL3 runtime service writer's guide (rt-svc-writers-guide.md) to ease creation of new runtime services. Change-Id: I670aeb5fc246e25c6e599a15139aac886a0074fd
2014-02-28Separate firmware design out of user-guide.mdDan Handley
Move the firmware design documentation out of user-guide.md and into a new file - firmware-design.md. Reformat the section headers. Change-Id: I664815dd47011c7c1cf2202aa4472a8fd78ebb92