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2016-05-29zynqmp: Remove double ';'Soren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-29zynqmp: Fix spelling of endiannessSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-27Merge pull request #632 from rockchip-linux/support-for-gpio-driver-v2danh-arm
rockchip/rk3399: Support the gpio driver and configure
2016-05-27rockchip: support system off function for rk3399Caesar Wang
if define power off gpio, BL31 will do system power off through gpio control.
2016-05-27rockchip: support reset SoC through gpio for rk3399Caesar Wang
If define a reset gpio, BL31 will use gpio to reset SOC, otherwise use CRU reset.
2016-05-27rockchip: add reset or power off gpio configuration for rk3399Caesar Wang
We add plat parameter structs to support BL2 to pass variable-length, variable-type parameters to BL31. The parameters are structured as a link list. During bl31 setup time, we travse the list to process each parameter. throuth this way, we can get the reset or power off gpio parameter, and do hardware control in BL31. This structure also can pass other parameter to BL31 in future.
2016-05-27rockchip: support rk3399 gpio driverCaesar Wang
There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs on rk3399 platform. The pull direction(pullup or pulldown) for all of GPIOs are software-programmable. At the moment, we add the gpio basic driver since reset or power off the devices from gpio configuration for BL31.
2016-05-25zynqmp: PSCI: Wait for FW completing wake requestsSoren Brinkmann
Powering up cores didn't wait for the PMUFW to complete the request, which could result in cores failing to power up in Linux. Reported-by: Koteswararao Nayudu <kotin@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-25Add CCN support to FVP platform portSoby Mathew
This patch adds support to select CCN driver for FVP during build. A new build option `FVP_INTERCONNECT_DRIVER` is added to allow selection between the CCI and CCN driver. Currently only the CCN-502 variant is supported on FVP. The common ARM CCN platform helper file now verifies the cluster count declared by platform is equal to the number of root node masters exported by the ARM Standard platform. Change-Id: I71d7b4785f8925ed499c153b2e9b9925fcefd57a
2016-05-24zynqmp: Ignore the revision field of the IDCODESoren Brinkmann
The revision field may change between silicon revisions without changing the mapping to a part. This avoids errors like: ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093 NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000 on parts with a newer revision. Reported-by: Love Kumar <love.kumar@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Love Kumar <love.kumar@xilinx.com>
2016-05-24zynqmp: Add bakery_lock to protect APU_PWRCTRL register accessStefan Krsmanovic
Access to APU_PWRCTRL register is protected during suspend/wakeup pocedure in order to save valid state. If more than one CPU is accessing this register it can be left in corrupted state during read-modify-write process. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-24zynqmp: Put pm_secure_lock in coherent memory regionStefan Krsmanovic
DEFINE_BAKERY_LOCK() macro is used to put lock in coherent memory region. ARM Trusted Firmware design guide, chapter 11 states that bakery_lock data structures should be allocated in coherent memory region because it is accessed by multiple CPUs with mismatched shareability, cacheability and memory attributes. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-24zynqmp: pm: Implement pm_register_notifier PM API functionAnes Hadziahmetagic
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-24zynqmp: pm: Implemented 'get_op_characteristic' PM API callAnes Hadziahmetagic
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-24zynqmp: pm: Removed double declaration of pm_ipi_send functionsFilip Drazic
Functions pm_ipi_send and pm_ipi_send_sync are declared in pm_ipi.h Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-05-24zynqmp: Reduce mapped memory areaSoren Brinkmann
The GIC area is specified larger than it needs to be and can be reduced. Which allows reducing the structures required for the translation tables as well. This results in a reduction of memory footprint of ca. 4k. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-05-20Replace Rockchip delay timer by generic oneAntonio Nino Diaz
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
2016-05-20Replace MediaTek delay timer by generic oneAntonio Nino Diaz
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e
2016-05-20Replace SP804 timer by generic delay timer on FVPAntonio Nino Diaz
Added a build flag to select the generic delay timer on FVP instead of the SP804 timer. By default, the generic one will be selected. The user guide has been updated. Change-Id: Ica34425c6d4ed95a187b529c612f6d3b26b78bc6
2016-05-20Implement plat_get_syscnt_freq2 on platformsAntonio Nino Diaz
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all upstream platforms. Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
2016-05-20Add 32 bit version of plat_get_syscnt_freqAntonio Nino Diaz
Added plat_get_syscnt_freq2, which is a 32 bit variant of the 64 bit plat_get_syscnt_freq. The old one has been flagged as deprecated. Common code has been updated to use this new version. Porting guide has been updated. Change-Id: I9e913544926c418970972bfe7d81ee88b4da837e
2016-05-12Merge pull request #622 from mtk09422/hw-crypt-v3danh-arm
Hw crypt v3
2016-05-12MT8173: Add Sip function for MTK HW crypt driverYi Zheng
Change-Id: Idc40cc6243e532567ec4334ae37d97c003c90bfa Signed-off-by: Yi Zheng <yi.zheng@mediatek.com>
2016-05-12mt8173: Reorganize plat SiP functionsJimmy Huang
Due to the changes in Mediatek platform common code, we need to move plat related SiP functions to plat folder. Change-Id: I6b14b988235205a5858b4bf49043bc79d0512b06 Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
2016-05-05Rockchip: Add some debug assertions in the PMU driverSandrine Bailleux
This patch adds some debug assertions ensuring that array indices are within the bounds of the array. Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a
2016-05-04Merge pull request #618 from rockchip-linux/fixes-for-suspend/resumedanh-arm
rockchip: support the suspend/resume for rk3399
2016-05-04Merge pull request #617 from leon-chen-mtk/refactor_common_1danh-arm
Refactor MediaTek platform common code
2016-05-04rockchip: support the suspend/resume for rk3399Caesar Wang
This patch adds to support the suspend/resume for rk3399 SoCs. Signed-off-by: Shengfei xu <xsf@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-05-04Refactor MediaTek platform common codeLeon Chen
Refactor MediaTek platform common code for further mt6795 upstream.
2016-04-28Change the default driver to GICv3 in FVPSoby Mathew
This patch changes the default driver for FVP platform from the deprecated GICv3 legacy to the GICv3 only driver. This means that the default build of Trusted Firmware will not be able boot Linux kernel with GICv2 FDT blob. The user guide is also updated to reflect this change of default GIC driver for FVP. Change-Id: Id6fc8c1ac16ad633dabb3cd189b690415a047764
2016-04-27Remove support for legacy VE memory map in FVPSoby Mathew
This patch removes support for legacy Versatile Express memory map for the GIC peripheral in the FVP platform. The user guide is also updated for the same. Change-Id: Ib8cfb819083aca359e5b46b5757cb56cb0ea6533
2016-04-26Conditionally compile `plat_get_syscnt_freq()` in ARM standard platformsYatharth Kochar
This patch puts the definition of `plat_get_syscnt_freq()` under `#ifdef ARM_SYS_CNTCTL_BASE` in arm_common.c file. This is the fix for compilation error introduced by commit-id `749ade4`, for platforms that use arm_common.c but do not provide a memory mapped interface to the generic counter. Fixes ARM-software/tf-issues#395 Change-Id: I2f2b10bd9500fa15308541ccb15829306a76a745
2016-04-25zynqmp: FSBL->ATF handoverMichal Simek
Parse the parameter structure the FSBL populates, to populate the bl32 and bl33 image structures. Cc: Sarat Chand Savitala <saratcha@xilinx.com> Cc: petalinux-dev@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> [ SB - pass pointers to structs instead of structs - handle execution state parameter - populate bl32 SPSR - add documentation - query bootmode and consider missing handoff parameters an error when not in JTAG boot mode ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-04-25zynqmp: Introduce zynqmp_get_bootmodeSoren Brinkmann
Provide a function to retrieve the bootmode. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-04-25zynqmp: Remove bogus commentSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-04-25zynqmp: Revise memory configuration optionsSoren Brinkmann
Drop the current configuration options for selecting the location of the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION). The new configuration provides one default setup (ATF in OCM, BL32 in DRAM). Additionally, the new configuration options - ZYNQMP_ATF_MEM_BASE - ZYNQMP_ATF_MEM_SIZE - ZYNQMP_BL32_MEM_BASE - ZYNQMP_BL32_MEM_SIZE can be used to freely configure the memory locations used for ATF and secure payload. Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE. Cc: petalinux-dev@xilinx.com Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
2016-04-25Merge pull request #602 from rockchip-linux/fixes-for-coreboot_v1danh-arm
rockchip: fixes for the required
2016-04-25rockchip: fixes for the requiredCaesar Wang
This patch has the following change for rk3399. * Set the uart to 115200 since the loader decide to set uart baud to 115200Hz. So the ATF also should set uart baud to 115200. * We need ensure the bl31 base is greater than 4KB since there are have the shared mem for coreboot.(Note: the previous vesion was tested with uboot) Otherwise, we will happen the exception crash since the ddr area won't to work from the shared ram address in some cases. For example, the exception crash: CBFS: Found @ offset 19c80 size 24074 exception _sync_sp_el0 ELR = 0x0000000000008000 ESR = 0x0000000002000000 SPSR = 0x600003cc FAR = 0xffffffff00000000 SP = 0x00000000ff8ed230 ... X29 = 0x00000000ff8c1fc0 X30 = 0x000000000030e3b0 exception death Change-Id: I8bc557c6bcaf6804d2a313b38667d3e2517881d7 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-04-21Move `plat_get_syscnt_freq()` to arm_common.cYatharth Kochar
This patch moves the definition for `plat_get_syscnt_freq()` from arm_bl31_setup.c to arm_common.c. This could be useful in case a delay timer needs to be installed based on the generic timer in other BLs. This patch also modifies the return type for this function from `uint64_t` to `unsigned long long` within ARM and other platform files. Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
2016-04-18zynqmp: ipi: Consolidate IRQ #definesSoren Brinkmann
The bit mapping in I(E|D|S)R are equal, consolidate the #defines. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-04-18zynqmp: Remove unused/redundant #includesSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-04-14Dump platform-defined regs in crash reportingGerald Lejeune
It is up to the platform to implement the new plat_crash_print_regs macro to report all relevant platform registers helpful for troubleshooting. plat_crash_print_regs merges or calls previously defined plat_print_gic_regs and plat_print_interconnect_regs macros for each existing platforms. NOTE: THIS COMMIT REQUIRES ALL PLATFORMS THAT ENABLE THE `CRASH_REPORTING` BUILD FLAG TO MIGRATE TO USE THE NEW `plat_crash_print_regs()` MACRO. BY DEFAULT, `CRASH_REPORTING` IS ENABLED IN DEBUG BUILDS FOR ALL PLATFORMS. Fixes: arm-software/tf-issues#373 Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
2016-04-14Merge pull request #593 from mtk09422/mtcmos-fixdanh-arm
mt8173: Fix timing issue of mfg mtcmos power off
2016-04-14mt8173: Fix timing issue of mfg mtcmos power offFan Chen
In mt8173, there are totally 10 non-cpu mtcmos, so we cannot tell if SPM finished the power control flow by 10 status bits of PASR_PDP_3. So, extend PASR_PDP_3 status bits from 10 to 20 so that we can make sure if the control action has been done precisely. Change-Id: Ifd4faaa4173c6e0543aa8471149adb9fe7fadedc Signed-off-by: Fan Chen <fan.chen@mediatek.com>
2016-04-13Migrate platform ports to the new xlat_tables librarySoby Mathew
This patch modifies the upstream platform port makefiles to use the new xlat_tables library files. This patch also makes mmap region setup common between AArch64 and AArch32 for FVP platform port. The file `fvp_common.c` is moved from the `plat/arm/board/fvp/aarch64` folder to the parent folder as it is not specific to AArch64. Change-Id: Id2e9aac45e46227b6f83cccfd1e915404018ea0b
2016-04-12Fix build error in Rockchip platformSoby Mathew
This patch fixes the compilation error in Rockchip rk3368 platform port when it is built in release mode. Fixes ARM-software/tf-issues#389 Change-Id: I1a3508ac3a620289cf700e79db8f08569331ac53
2016-04-08Merge pull request #569 from Xilinx/zynqmp-v1danh-arm
Support for Xilinx Zynq UltraScale+ MPSoC
2016-04-08Merge pull request #587 from antonio-nino-diaz-arm/an/rename-bl33-basedanh-arm
Rename BL33_BASE and make it work with RESET_TO_BL31
2016-04-08Merge pull request #586 from antonio-nino-diaz-arm/an/spd-bl32danh-arm
Remove BL32_BASE when building without SPD for FVP
2016-04-08Rename BL33_BASE option to PRELOADED_BL33_BASEAntonio Nino Diaz
To avoid confusion the build option BL33_BASE has been renamed to PRELOADED_BL33_BASE, which is more descriptive of what it does and doesn't get mistaken by similar names like BL32_BASE that work in a completely different way. NOTE: PLATFORMS USING BUILD OPTION `BL33_BASE` MUST CHANGE TO THE NEW BUILD OPTION `PRELOADED_BL33_BASE`. Change-Id: I658925ebe95406edf0325f15aa1752e1782aa45b
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