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2017-04-02platform: Add support for Marvell A7K/A8K platformsKonstantin Porotchkin
Add platform support files for Marvell A7K and A7K SoC families. Change-Id: I4f8b0a7cd222be5b7f43577172f1cdba58ffc124 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37918
2017-04-02platform: Add marvell platforms common componentsKonstantin Porotchkin
Add common platform components to be used by all supported Marvell platforms. Change-Id: Ie5f70fc7ff668c8f8073d6dd936458f35890ebcf Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38133
2016-09-26Merge pull request #717 from sandrine-bailleux-arm/sb/foundation-fvp-v10davidcunado-arm
Whitelist version 9.6 of Foundation FVP
2016-09-23Whitelist version 9.6 of Foundation FVPSandrine Bailleux
This prevents a warning being emitted in the console during FVP configuration setup when using the Foundation FVP 9.6 onwards. Change-Id: I685b8bd0dbd0119af4b0cb3f7d708fcc08e99561
2016-09-21AArch32: Add support for ARM Cortex-A32 MPCore ProcessorYatharth Kochar
This patch adds ARM Cortex-A32 MPCore Processor support in the CPU specific operations framework. It also includes this support for the Base FVP port. Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d
2016-09-21AArch32: Support in SP_MIN to receive arguments from BL2Yatharth Kochar
This patch adds support in SP_MIN to receive generic and platform specific arguments from BL2. The new signature is as following: void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2); ARM platforms have been modified to use this support. Note: Platforms may break if using old signature. Default value for RESET_TO_SP_MIN is changed to 0. Change-Id: I008d4b09fd3803c7b6231587ebf02a047bdba8d0
2016-09-21AArch32: Add ARM platform changes in BL2Yatharth Kochar
This patch adds ARM platform changes in BL2 for AArch32 state. It instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL32` and `BL33`. It also enables building of BL2 for ARCH=aarch32. Change-Id: I60dc7a284311eceba401fc789311c50ac746c51e
2016-09-21AArch32: Add ARM platform changes in BL1Yatharth Kochar
This patch adds ARM platform changes in BL1 for AArch32 state. It also enables building of BL1 for ARCH=aarch32. Change-Id: I079be81a93d027f37b0f7d8bb474b1252bb4cf48
2016-09-21AArch32: Common changes needed for BL1/BL2Yatharth Kochar
This patch adds common changes to support AArch32 state in BL1 and BL2. Following are the changes: * Added functions for disabling MMU from Secure state. * Added AArch32 specific SMC function. * Added semihosting support. * Added reporting of unhandled exceptions. * Added uniprocessor stack support. * Added `el3_entrypoint_common` macro that can be shared by BL1 and BL32 (SP_MIN) BL stages. The `el3_entrypoint_common` is similar to the AArch64 counterpart with the main difference in the assembly instructions and the registers that are relevant to AArch32 execution state. * Enabled `LOAD_IMAGE_V2` flag in Makefile for `ARCH=aarch32` and added check to make sure that platform has not overridden to disable it. Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
2016-09-21ARM platform changes for new version of image loadingYatharth Kochar
This patch adds changes in ARM platform code to use new version of image loading. Following are the major changes: -Refactor the signatures for bl31_early_platform_setup() and arm_bl31_early_platform_setup() function to use `void *` instead of `bl31_params_t *`. -Introduce `plat_arm_bl2_handle_scp_bl2()` to handle loading of SCP_BL2 image from BL2. -Remove usage of reserve_mem() function from `arm_bl1_early_platform_setup()` -Extract BL32 & BL33 entrypoint info, from the link list passed by BL2, in `arm_bl31_early_platform_setup()` -Provides weak definitions for following platform functions: plat_get_bl_image_load_info plat_get_next_bl_params plat_flush_next_bl_params bl2_plat_handle_post_image_load -Instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL31`, `BL32` and `BL33` images. All the above changes are conditionally compiled using the `LOAD_IMAGE_V2` flag. Change-Id: I5e88b9785a3df1a2b2bbbb37d85b8e353ca61049
2016-09-19Merge pull request #711 from leon-chen-mtk/mt6795_2danh-arm
Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.
2016-09-19Merge pull request #702 from jeenu-arm/psci-node-hw-statedanh-arm
Support for PSCI NODE_HW_STATE
2016-09-19Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.Leon Chen
2016-09-16Merge pull request #709 from Xilinx/zynqmp-2016-09davidcunado-arm
xilinx: ZynqMP updates - new SIP calls for bitstream programming - new SIP call to discover the SOC silicon version - support the delay timer
2016-09-15CSS: Implement support for NODE_HW_STATEJeenu Viswambharan
This patch implements CSS platform hook to support NODE_HW_STATE PSCI API. The platform hook queries SCP to obtain CSS power state. Power states returned by SCP are then converted to expected PSCI return codes. Juno's PSCI operation structure is modified to use the CSS implementation. Change-Id: I4a5edac0e5895dd77b51398cbd78f934831dafc0
2016-09-15SCPI: Add function to query CSS power stateJeenu Viswambharan
This patch adds the function scpi_get_css_power_state to perform the 'Get CSS Power State' SCP command and handle its response. The function parses SCP response to obtain power states of requested cluster and CPUs within. Change-Id: I3ea26e48dff1a139da73f6c1e0893f21accaf9f0
2016-09-15FVP: Implement support for NODE_HW_STATEJeenu Viswambharan
This patch implements FVP platform hook to support NODE_HW_STATE PSCI API. The platform hook validates the given MPIDR and reads corresponding status from FVP power controller, and returns expected values for the PSCI call. Change-Id: I286c92637da11858db2c8aba8ba079389032de6d
2016-09-14Merge pull request #663 from leon-chen-mtk/mt6795_2davidcunado-arm
mediatek: Support for Mediatek MT6795 SoC
2016-09-14Merge pull request #700 from rockchip-linux/fixes-typo-and-warningsdavidcunado-arm
rockchip: Fixes typo and warnings
2016-09-13zynqmp: Make MMIO write FW call synchronousSoren Brinkmann
We must guarantee that writes have become effective before returning to the caller. Hence, wait for PMUFW signaling completion of the FW call before returning to the rich OS. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Add support to provide silicon id through SMCSiva Durga Prasad Paladugu
Add support to provide silicon id to non-secure software through SMC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [ sb Move zynqmp_get_silicon_id outside of compile guards to avoid build errors. ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-13zynqmp: pm: Implemented pm API functions to load the bitstream into PLNava kishore Manne
This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide the Access to the xilfpga library to load the bitstream into zynqmp PL region. Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2016-09-13zynqmp: pm: adds new pm ID to sync with PMUFW ID numbersNava kishore Manne
This patch adds a new pm ID to sync with PMUFW ID numbers. Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2016-09-13zynqmp: Initialize GIC on suspend_finishSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: pm: Call set_wakeup_source for all wake devices on sys-suspendFilip Drazic
During system suspend, identify slaves which are configured as wake sources and call pm_set_wakeup_source API for each of them. Identifying if device may wake the system is done by checking if any interrupt of that device is enabled in GICD_ISENABLER when the APU is about to enter SUSPEND_TO_RAM state. If such interrupt is found, pm_set_wakeup_source is called with corresponding PM node ID as argument. Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2016-09-13zynqmp: pm: Add PM node IDs for GPU, PCIE, PCAP and RTCFilip Drazic
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2016-09-13zynqmp: pm: Provide state argument to the pm_self_suspend API callFilip Drazic
The state argument of the pm_self_suspend API encodes the state to which the APU intends to suspend. The state can be: - PM_APU_STATE_CPU_IDLE - processor power down, all memories remain on - PM_APU_STATE_SUSPEND_TO_RAM - all processors powered down, L2$ powered down, all OCM banks in retention and DDR in self-refresh. The calls for setting requirements for L2$ and OCM banks are now redundant and removed. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> [ sb - remove redundant #defines ] Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Add simple implementation of zynqmp_validate_power_state()Stefan Krsmanovic
Implementation is based on arm_validate_power_state(). This function is called during CPU_SUSPEND PSCI call to validate power_state parameter. If state is valid this function populate it in req_state array as power domain level specific local state. ATF platform migration guide chapter 2.2 defines this function as mandatory for PSCIv1.0 CPU_SUSPEND support. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
2016-09-13zynqmp: Increase MAX_XLAT_TABLESSoren Brinkmann
When moving the ATF into the DRAM address space an additional translation table is required. Reported-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Change default BL31 address spaceSoren Brinkmann
The OCM space was reorganized to use the space more efficiently. Adjust the default ATF location to be aligned with other ZynqMP software components. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1Naga Sureshkumar Relli
Arm provided error injection support. To enable this error injection, we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in CPUACTLR_EL1 register. This is needed for our cortexa53 edac linux driver testing. These registers need write access from non secure EL1 i.e linux at the time of setting the above bits. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
2016-09-13zynqmp: Set RESET_TO_BL31 through platform.mkSoren Brinkmann
ZynqMP only supports builds with RESET_TO_BL31=1. Set this option through the platform makefile on default. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: pm: Added NODE_IPI_RPU_0 node definition in pm_defsMirela Simonovic
Nodes represent IPI dedicated to the RPU (not accessible by APU) Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
2016-09-13zynqmp: Add support for generic_delay_timerSoren Brinkmann
Initialize the generic_delay_timer in the zynqmp port. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13rockchip: fixes the gic panic for rk3399 resumeCaesar Wang
We make sure the resuming of gic need to be enabled. Otherwise, The resume will hit the below panic. ... [ 24.230541] CPU0: update max cpu_capacity 451 [ 24.236029] CPU5: update max cpu_capacity 1024 [ 24.236046] CPU4: shutdown [ 24.243205] psci: CPU4 killed. [ 24.258730] CPU5: shutdown [ 24.261472] psci: CPU5 killed. [ 24.270417] GIC: unable to set SRE (disabled at EL2), panic ahead [ 24.270417] cat[7801]: undefined instruction: pc=ffffffc0004e65d0 [ 24.270417] Code: b0003940 91274400 97f871af d2801e00 (d5184600) [ 24.270417] Internal error: Oops - undefined instruction: 0 [#1] PREEMPT Change-Id: Ie9542c8d5768ba0accfa073453da8bfe06d4f921
2016-09-12Support for Mediatek MT6795 SoCLeon Chen
This patch support single core to boot to Linux kernel through Trusted Firmware. It also support 32 bit kernel and 64 bit kernel booting.
2016-09-10rockchip: fixes some typoCaesar Wang
As the checkpatch reports the warning or error. plat/rockchip/common/plat_pm.c:96: ERROR: do not set execute permissions for source files plat/rockchip/rk3399/drivers/pmu/pmu.c:294: ERROR: do not set execute permissions for source files plat/rockchip/common/plat_pm.c:286: WARNING: line over 80 characters plat/rockchip/common/plat_pm.c:287: WARNING: line over 80 characters Change-Id: Ib347da21c56551c31df3f90f03777b13c75d5c26
2016-09-10rockchip: SIP call use 32 bit return value for rk3399Caesar Wang
for compatible 32bit and 64bit, we use 0x82xxxxxx as function ID, we modify SIP call function return value to 32 bit. Change-Id: Ib99b03a9ea423853aaa296dcc634ee82c622a552
2016-09-10rockchip: set gpio2 ~ gpio4 to input and pull none modeCaesar Wang
For save power cosumption, if gpio power supply shut down, we need to set gpio2 ~ gpio4 to input and HiZ status when suspend, and recovery they status when rusume. we do it base on apio pass from loader. Change-Id: I59fd2395e5e37e63425472a39f519822c9197e4c
2016-09-10rockchip: support disable/enable specific gpio when suspend/resumeCaesar Wang
some specific board need to disable/enable specific gpio when suspend/resume, so we add this function, bootloader can pass the specific gpio, and we can handle these gpios in bl31 suspend/resuem function. Change-Id: I373b03ef9202ee4a05a2b9caacdfa01b47ee2177
2016-09-10rockchip/rk3399: improve gpio driver and support get pull mode functionCaesar Wang
We may need gpio pull mode later, so add this function. Besides fix a set pull mode bug, and save gpio clock gate, when operate the gpio, we will enable gpio clock, when finish gpio operate, restore gpio clock gate status. Change-Id: Ia1d602804f571a17f5ddc499908663b968b02974
2016-09-08rockchip: fix the scu idle for rk3399Tony Xie
As rk3399 reported the d8/octane scores drop 10% with cpu idle. The root cause is thc cpu cluster enter the slow mode. We don't need switch the clock to 24MHz if cpu cluster enter the retention mode. In order to improve performance, it just needs for cluster enter powering off mode. Also, we shouldn't do anything for hlvl if the system is off. Change-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119
2016-08-26Merge pull request #691 from rockchip-linux/fixes-suspend/resume-bugsdavidcunado-arm
Fixes suspend/resume bugs
2016-08-25Merge pull request #684 from rockchip-linux/add-sdram-for-rk3399davidcunado-arm
rockchip: add dram driver for rk3399
2016-08-25rockchip: handle some interrupt before enter power mode for rk3399Caesar Wang
For the PMU design, we don't expect to get the interrupts before enter the power mode. Since that will cause the confusion for the state machine in the power mode. Change-Id: Id8dee79ae617a66271b5caf92caf35f520f45099
2016-08-25rockchip: remove the unused code for rk3399Caesar Wang
Change-Id: I986d64df9dc62354d50ccea0468b90f090a44160 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-08-25rockchip: on rk3399 enable Schmitt trigger on 32 kHz clockCaesar Wang
If we don't enable the Schmitt trigger on the 32 kHz clock then systems won't always resume from suspend properly. Presumably anything else in the system that relies on the 32 kHz clock also will have problems without the Schmitt trigger enabled. Enable it always since having the 32 kHz clock on GPIO0_A0 isn't exactly an optional feature, so all boards using rk3399 will need this. Change-Id: Idc18c6cd1adc5be5f60efd9cb805d83d5cd40129
2016-08-25rockchip: enable or disable auto power down base on frequencyCaesar Wang
add auto_pd_dis_freq parameter, we can pass a frequency from kernel to disable or enable ddr auto power down function. Change-Id: Ie30914701336c59047c380381c6b75dd76a89562
2016-08-25rockchip: rk3399: add dram driverCaesar Wang
add dram driver, and kernel can through sip function talk to bl31 to do ddr frequency scaling. and ddr auto powerdown. Change-Id: I0d0f2869aed95e336c6e23ba96a9310985c84840
2016-08-25rockchip: on rk3399 init the PMU counts at boot; set 24M/32k properlyCaesar Wang
In a previous change we mistakenly thought that PMU_24M_EN_CFG directly controlled whether the PMU counts ran off the 32k vs. 24M clock. Apparently that's not true. Real logic is now documented in code. Also in the previous change we mistaknely though that PMU_24M_EN_CFG was normally supposed to be 1 and we should "restore" it at resume time. This is a terrible idea and made the system totally unreliable after resume. Apparently PMU_24M_EN_CFG should always be 0 with all the current code and settings. Let's fix the above two problems. While we're changing all of this, let's also: 1. Init at boot time. Many of these counts are used when the system is running normally. We want the behavior at boot to match the behavior after suspend/resume. 2. Init CPU counts to be 1 us. Although old code was trying to set this to 1 ms (1000x slower) at suspend/resume time, we've been testing the kernel with 1 us for a long time now. That's because the kernel (at boot time) set these values to 24. Let's keep at 24 until we know that's wrong. 3. Init GPU counts to be 1 us. Old code wasn't touching the GPU, but as documented in comments it makes sense to init here. Do it. 4. Document the crap out of this code, since the SoC's behavior is confusing and poorly documented in the TRM. 5. Increase some stabilization times to 30 ms (from 3 ms). It's unclear that a full 30 ms is needed, but let's be safe for now. This also inits the counts for the GPU. (Thanks to Doug's patch that come from https://crosreview.com/372381) Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22
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