etna: figure out some texture formats

DXT3/DXT5 works, but DXT1 is behaving somewhat strangely

10 files changed, 468 insertions, 361 deletions

diff --git a/envytools/rnn/headergen.c b/envytools/rnn/headergen.c
index 79d81d9..5113c14 100644
--- a/envytools/rnn/headergen.c
+++ b/envytools/rnn/headergen.c
@@ -107,7 +107,7 @@ void printdef (char *name, char *suf, int type, uint64_t val, char *file) {
 			fprintf (dst, "%"PRIu64"\n", val);
 			break;
                 case 2:
-			fprintf (dst, "((x) << %"PRIu64")\n", val);
+			fprintf (dst, "(((x) << %s__SHIFT) & %s__MASK)\n", name, name);
                         break;
 	}
 }
diff --git a/native/fb/exec_fb.sh b/native/fb/exec_fb.sh
index b735c02..d6b7da7 100755
--- a/native/fb/exec_fb.sh
+++ b/native/fb/exec_fb.sh
@@ -5,8 +5,23 @@ if [ -z "$DEMO" ]; then
     DEMO="fbtest"
     echo "Defaulting to ${DEMO}"
 fi
-ARG=/data/mine/shader.bin
+if [[ "$DEMO" == "ps_sandbox_etna" || "$DEMO" == "etna_test" ]]; then
+    ARG="/data/mine/shader.bin"
+    ../../tools/asm.py ../../rnndb/isa.xml sandbox.asm -o shader.bin
+    [ $? -ne 0 ] && exit
+    adb push shader.bin ${ARG}
+fi
+if [[ "$DEMO" == "mip_cube" ]]; then
+    #TEX="mipdxt1"
+    #TEX="test_image-dxt3"
+    TEX="mipdxt5"
+    #TEX="test_image-dxt1a"
+    #TEX="test_image-dxt1c"
+    adb push ../resources/${TEX}.dds /mnt/sdcard
+    ARG="/mnt/sdcard/${TEX}.dds"
+fi
 make ${DEMO}
+[ $? -ne 0 ] && exit
 adb push ${DEMO} /data/mine
 adb shell "/data/mine/${DEMO} ${ARG}"
 #adb pull /mnt/sdcard/egl2.fdr .
diff --git a/native/fb/mip_cube.c b/native/fb/mip_cube.c
index c65419c..a0056d4 100644
--- a/native/fb/mip_cube.c
+++ b/native/fb/mip_cube.c
@@ -32,6 +32,7 @@
 #include <sys/mman.h>
 #include <stdarg.h>
 #include <assert.h>
+#include <math.h>
 
 #include <errno.h>
 
@@ -48,6 +49,7 @@
 #include "esUtil.h"
 #include "dds.h"
 
+#define RCPLOG2 (1.4426950408889634f)
 #define VERTEX_BUFFER_SIZE 0x60000
 
 float vVertices[] = {
@@ -260,7 +262,7 @@ int main(int argc, char **argv)
     size_t z_ts_size = etna_align_up((padded_width * padded_height * 2)/0x100, 0x100);
 
     dds_texture *dds = 0;
-    if(!dds_load("/mnt/sdcard/miprgba.dds", &dds))
+    if(argc<2 || !dds_load(argv[1], &dds))
     {
         printf("Error loading texture\n");
         exit(1);
@@ -280,13 +282,35 @@ int main(int argc, char **argv)
         exit(1);
     }
 
-    //memcpy(tex->logical, dds->data, dds->size);
-    assert(dds->fmt == FMT_X8R8G8B8 || dds->fmt == FMT_A8R8G8B8);
-    for(int ix=0; ix<dds->num_mipmaps; ++ix)
+    uint32_t tex_format = 0;
+    uint32_t tex_base_width = dds->slices[0][0].width;
+    uint32_t tex_base_height = dds->slices[0][0].height;
+    uint32_t tex_base_log_width = (int)(logf(tex_base_width) * RCPLOG2 * 32.0f + 0.5f);
+    uint32_t tex_base_log_height = (int)(logf(tex_base_height) * RCPLOG2 * 32.0f + 0.5f);
+    printf("Loading compressed texture (format %i, %ix%i) log_width=%i log_height=%i\n", dds->fmt, width, height, tex_base_log_width, tex_base_log_height);
+    if(dds->fmt == FMT_X8R8G8B8 || dds->fmt == FMT_A8R8G8B8)
     {
-        printf("%08x: Tiling mipmap %i (%ix%i)\n", dds->slices[0][ix].offset, ix, dds->slices[0][ix].width, dds->slices[0][ix].height);
-        tile_texture((void*)((size_t)tex->logical + dds->slices[0][ix].offset), 
-                dds->slices[0][ix].data, dds->slices[0][ix].width, dds->slices[0][ix].height, dds->slices[0][ix].stride, 4);
+        for(int ix=0; ix<dds->num_mipmaps; ++ix)
+        {
+            printf("%08x: Tiling mipmap %i (%ix%i)\n", dds->slices[0][ix].offset, ix, dds->slices[0][ix].width, dds->slices[0][ix].height);
+            tile_texture((void*)((size_t)tex->logical + dds->slices[0][ix].offset), 
+                    dds->slices[0][ix].data, dds->slices[0][ix].width, dds->slices[0][ix].height, dds->slices[0][ix].stride, 4);
+        }
+        tex_format = TEXTURE_FORMAT_X8R8G8B8;
+    } else if(dds->fmt == FMT_DXT1 || dds->fmt == FMT_DXT3 || dds->fmt == FMT_DXT5)
+    {
+        printf("Loading compressed texture\n");
+        memcpy(tex->logical, dds->data, dds->size);
+        switch(dds->fmt)
+        {
+        case FMT_DXT1: tex_format = TEXTURE_FORMAT_DXT1;
+        case FMT_DXT3: tex_format = TEXTURE_FORMAT_DXT2_DXT3;
+        case FMT_DXT5: tex_format = TEXTURE_FORMAT_DXT4_DXT5;
+        }
+    } else
+    {
+        printf("Unknown texture format\n");
+        exit(1);
     }
 
     /* Phew, now we got all the memory we need.
@@ -478,11 +502,11 @@ int main(int argc, char **argv)
         /* set up texture unit */
         etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_TEXTURE);
         etna_set_state(ctx, VIVS_TE_SAMPLER_SIZE(0), 
-                VIVS_TE_SAMPLER_SIZE_WIDTH(256)| // XXX don't hardcode this size
-                VIVS_TE_SAMPLER_SIZE_HEIGHT(256));
+                VIVS_TE_SAMPLER_SIZE_WIDTH(tex_base_width)|
+                VIVS_TE_SAMPLER_SIZE_HEIGHT(tex_base_height));
         etna_set_state(ctx, VIVS_TE_SAMPLER_LOG_SIZE(0), 
-                VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(8<<5) |
-                VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(8<<5));
+                VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(tex_base_log_width) |
+                VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(tex_base_log_height));
         for(int ix=0; ix<dds->num_mipmaps; ++ix)
         {
             etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_ADDR(0,ix), tex->address + dds->slices[0][ix].offset);
@@ -494,7 +518,7 @@ int main(int argc, char **argv)
                 VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_LINEAR)|
                 VIVS_TE_SAMPLER_CONFIG0_MIP(TEXTURE_FILTER_LINEAR)|
                 VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_LINEAR)|
-                VIVS_TE_SAMPLER_CONFIG0_FORMAT(TEXTURE_FORMAT_X8R8G8B8));
+                VIVS_TE_SAMPLER_CONFIG0_FORMAT(tex_format));
         etna_set_state(ctx, VIVS_TE_SAMPLER_LOD_CONFIG(0), 
                 VIVS_TE_SAMPLER_LOD_CONFIG_MAX((dds->num_mipmaps - 1)<<5) | VIVS_TE_SAMPLER_LOD_CONFIG_MIN(0));
 
@@ -504,7 +528,9 @@ int main(int argc, char **argv)
         etna_set_state_multi(ctx, VIVS_VS_INPUT_COUNT, 3, (uint32_t[]){
                 /* VIVS_VS_INPUT_COUNT */ VIVS_VS_INPUT_COUNT_UNK8(1) | VIVS_VS_INPUT_COUNT_COUNT(3),
                 /* VIVS_VS_TEMP_REGISTER_CONTROL */ VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(6),
-                /* VIVS_VS_OUTPUT(0) */ 0x10004}); /* 0x00004 causes wrong texture coordinates */
+                /* VIVS_VS_OUTPUT(0) */ VIVS_VS_OUTPUT_O0(4) | 
+                                        VIVS_VS_OUTPUT_O1(0) | 
+                                        VIVS_VS_OUTPUT_O2(1)});
         etna_set_state_multi(ctx, VIVS_VS_INST_MEM(0), vs_size/4, vs);
         etna_set_state(ctx, VIVS_RA_CONTROL, 0x3);
         etna_set_state(ctx, VIVS_PS_START_PC, 0x0);
@@ -534,7 +560,7 @@ int main(int argc, char **argv)
         etna_set_state_multi(ctx, VIVS_PS_INST_MEM(0), ps_size/4, ps);
         etna_set_state(ctx, VIVS_VS_OUTPUT_COUNT, 3);
         etna_set_state(ctx, VIVS_PS_INPUT_COUNT, VIVS_PS_INPUT_COUNT_UNK8(31) | VIVS_PS_INPUT_COUNT_COUNT(3));
-        etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL, (3 << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT));
+        etna_set_state(ctx, VIVS_PS_TEMP_REGISTER_CONTROL, VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(3));
         etna_set_state(ctx, VIVS_PS_CONTROL, VIVS_PS_CONTROL_UNK1);
         etna_set_state(ctx, VIVS_VS_LOAD_BALANCING, 0xf3f0542); /* depends on number of inputs/outputs/varyings? XXX how exactly */
         
@@ -601,7 +627,9 @@ int main(int argc, char **argv)
                 VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF |
                 VIVS_FE_VERTEX_ELEMENT_CONFIG_START(0x18) |
                 VIVS_FE_VERTEX_ELEMENT_CONFIG_END(0x20));
-        etna_set_state(ctx, VIVS_VS_INPUT(0), 0x20100);
+        etna_set_state(ctx, VIVS_VS_INPUT(0), VIVS_VS_INPUT_I0(0) | 
+                                        VIVS_VS_INPUT_I1(1) | 
+                                        VIVS_VS_INPUT_I2(2));
         etna_set_state(ctx, VIVS_PA_CONFIG, ETNA_MASKED_BIT(VIVS_PA_CONFIG_POINT_SPRITE_ENABLE, 0));
 
         for(int prim=0; prim<6; ++prim)
diff --git a/native/include/etna/cmdstream.xml.h b/native/include/etna/cmdstream.xml.h
index d95cb5a..5f5cede 100644
--- a/native/include/etna/cmdstream.xml.h
+++ b/native/include/etna/cmdstream.xml.h
@@ -47,10 +47,10 @@ Copyright (C) 2013
 #define VIV_FE_LOAD_STATE_HEADER_FIXP				0x04000000
 #define VIV_FE_LOAD_STATE_HEADER_COUNT__MASK			0x03ff0000
 #define VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT			16
-#define VIV_FE_LOAD_STATE_HEADER_COUNT(x)			((x) << 16)
+#define VIV_FE_LOAD_STATE_HEADER_COUNT(x)			(((x) << VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT) & VIV_FE_LOAD_STATE_HEADER_COUNT__MASK)
 #define VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK			0x0000ffff
 #define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT			0
-#define VIV_FE_LOAD_STATE_HEADER_OFFSET(x)			((x) << 0)
+#define VIV_FE_LOAD_STATE_HEADER_OFFSET(x)			(((x) << VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT) & VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK)
 #define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR			2
 
 #define VIV_FE_END						0x00000000
@@ -58,7 +58,7 @@ Copyright (C) 2013
 #define VIV_FE_END_HEADER					0x00000000
 #define VIV_FE_END_HEADER_EVENT_ID__MASK			0x0000001f
 #define VIV_FE_END_HEADER_EVENT_ID__SHIFT			0
-#define VIV_FE_END_HEADER_EVENT_ID(x)				((x) << 0)
+#define VIV_FE_END_HEADER_EVENT_ID(x)				(((x) << VIV_FE_END_HEADER_EVENT_ID__SHIFT) & VIV_FE_END_HEADER_EVENT_ID__MASK)
 #define VIV_FE_END_HEADER_EVENT_ENABLE				0x00000100
 #define VIV_FE_END_HEADER_OP__MASK				0xf8000000
 #define VIV_FE_END_HEADER_OP__SHIFT				27
@@ -76,10 +76,10 @@ Copyright (C) 2013
 #define VIV_FE_DRAW_2D_HEADER					0x00000000
 #define VIV_FE_DRAW_2D_HEADER_COUNT__MASK			0x0000ff00
 #define VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT			8
-#define VIV_FE_DRAW_2D_HEADER_COUNT(x)				((x) << 8)
+#define VIV_FE_DRAW_2D_HEADER_COUNT(x)				(((x) << VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_COUNT__MASK)
 #define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK			0x07ff0000
 #define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT			16
-#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT(x)			((x) << 16)
+#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT(x)			(((x) << VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK)
 #define VIV_FE_DRAW_2D_HEADER_OP__MASK				0xf8000000
 #define VIV_FE_DRAW_2D_HEADER_OP__SHIFT				27
 #define VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D			0x20000000
@@ -87,18 +87,18 @@ Copyright (C) 2013
 #define VIV_FE_DRAW_2D_TOP_LEFT					0x00000004
 #define VIV_FE_DRAW_2D_TOP_LEFT_X__MASK				0x0000ffff
 #define VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT			0
-#define VIV_FE_DRAW_2D_TOP_LEFT_X(x)				((x) << 0)
+#define VIV_FE_DRAW_2D_TOP_LEFT_X(x)				(((x) << VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_X__MASK)
 #define VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK				0xffff0000
 #define VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT			16
-#define VIV_FE_DRAW_2D_TOP_LEFT_Y(x)				((x) << 16)
+#define VIV_FE_DRAW_2D_TOP_LEFT_Y(x)				(((x) << VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK)
 
 #define VIV_FE_DRAW_2D_BOTTOM_RIGHT				0x00000008
 #define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK			0x0000ffff
 #define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT			0
-#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(x)			((x) << 0)
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(x)			(((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK)
 #define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK			0xffff0000
 #define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT			16
-#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(x)			((x) << 16)
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(x)			(((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK)
 
 #define VIV_FE_DRAW_PRIMITIVES					0x00000000
 
@@ -110,7 +110,7 @@ Copyright (C) 2013
 #define VIV_FE_DRAW_PRIMITIVES_COMMAND				0x00000004
 #define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK		0x000000ff
 #define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT		0
-#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE(x)			((x) << 0)
+#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE(x)			(((x) << VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK)
 
 #define VIV_FE_DRAW_PRIMITIVES_START				0x00000008
 
@@ -126,7 +126,7 @@ Copyright (C) 2013
 #define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND			0x00000004
 #define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK	0x000000ff
 #define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT	0
-#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE(x)		((x) << 0)
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE(x)		(((x) << VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK)
 
 #define VIV_FE_DRAW_INDEXED_PRIMITIVES_START			0x00000008
 
@@ -139,7 +139,7 @@ Copyright (C) 2013
 #define VIV_FE_WAIT_HEADER					0x00000000
 #define VIV_FE_WAIT_HEADER_DELAY__MASK				0x0000ffff
 #define VIV_FE_WAIT_HEADER_DELAY__SHIFT				0
-#define VIV_FE_WAIT_HEADER_DELAY(x)				((x) << 0)
+#define VIV_FE_WAIT_HEADER_DELAY(x)				(((x) << VIV_FE_WAIT_HEADER_DELAY__SHIFT) & VIV_FE_WAIT_HEADER_DELAY__MASK)
 #define VIV_FE_WAIT_HEADER_OP__MASK				0xf8000000
 #define VIV_FE_WAIT_HEADER_OP__SHIFT				27
 #define VIV_FE_WAIT_HEADER_OP_WAIT				0x38000000
@@ -149,7 +149,7 @@ Copyright (C) 2013
 #define VIV_FE_LINK_HEADER					0x00000000
 #define VIV_FE_LINK_HEADER_PREFETCH__MASK			0x0000ffff
 #define VIV_FE_LINK_HEADER_PREFETCH__SHIFT			0
-#define VIV_FE_LINK_HEADER_PREFETCH(x)				((x) << 0)
+#define VIV_FE_LINK_HEADER_PREFETCH(x)				(((x) << VIV_FE_LINK_HEADER_PREFETCH__SHIFT) & VIV_FE_LINK_HEADER_PREFETCH__MASK)
 #define VIV_FE_LINK_HEADER_OP__MASK				0xf8000000
 #define VIV_FE_LINK_HEADER_OP__SHIFT				27
 #define VIV_FE_LINK_HEADER_OP_LINK				0x40000000
@@ -166,17 +166,17 @@ Copyright (C) 2013
 #define VIV_FE_STALL_TOKEN					0x00000004
 #define VIV_FE_STALL_TOKEN_FROM__MASK				0x0000001f
 #define VIV_FE_STALL_TOKEN_FROM__SHIFT				0
-#define VIV_FE_STALL_TOKEN_FROM(x)				((x) << 0)
+#define VIV_FE_STALL_TOKEN_FROM(x)				(((x) << VIV_FE_STALL_TOKEN_FROM__SHIFT) & VIV_FE_STALL_TOKEN_FROM__MASK)
 #define VIV_FE_STALL_TOKEN_TO__MASK				0x00001f00
 #define VIV_FE_STALL_TOKEN_TO__SHIFT				8
-#define VIV_FE_STALL_TOKEN_TO(x)				((x) << 8)
+#define VIV_FE_STALL_TOKEN_TO(x)				(((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
 
 #define VIV_FE_CALL						0x00000000
 
 #define VIV_FE_CALL_HEADER					0x00000000
 #define VIV_FE_CALL_HEADER_PREFETCH__MASK			0x0000ffff
 #define VIV_FE_CALL_HEADER_PREFETCH__SHIFT			0
-#define VIV_FE_CALL_HEADER_PREFETCH(x)				((x) << 0)
+#define VIV_FE_CALL_HEADER_PREFETCH(x)				(((x) << VIV_FE_CALL_HEADER_PREFETCH__SHIFT) & VIV_FE_CALL_HEADER_PREFETCH__MASK)
 #define VIV_FE_CALL_HEADER_OP__MASK				0xf8000000
 #define VIV_FE_CALL_HEADER_OP__SHIFT				27
 #define VIV_FE_CALL_HEADER_OP_CALL				0x50000000
diff --git a/native/include/etna/isa.xml.h b/native/include/etna/isa.xml.h
index 914d7af..5dca3dd 100644
--- a/native/include/etna/isa.xml.h
+++ b/native/include/etna/isa.xml.h
@@ -88,104 +88,104 @@ Copyright (C) 2013
 #define INST_COMPS_W						0x00000008
 #define INST_SWIZ_X__MASK					0x00000003
 #define INST_SWIZ_X__SHIFT					0
-#define INST_SWIZ_X(x)						((x) << 0)
+#define INST_SWIZ_X(x)						(((x) << INST_SWIZ_X__SHIFT) & INST_SWIZ_X__MASK)
 #define INST_SWIZ_Y__MASK					0x0000000c
 #define INST_SWIZ_Y__SHIFT					2
-#define INST_SWIZ_Y(x)						((x) << 2)
+#define INST_SWIZ_Y(x)						(((x) << INST_SWIZ_Y__SHIFT) & INST_SWIZ_Y__MASK)
 #define INST_SWIZ_Z__MASK					0x00000030
 #define INST_SWIZ_Z__SHIFT					4
-#define INST_SWIZ_Z(x)						((x) << 4)
+#define INST_SWIZ_Z(x)						(((x) << INST_SWIZ_Z__SHIFT) & INST_SWIZ_Z__MASK)
 #define INST_SWIZ_W__MASK					0x000000c0
 #define INST_SWIZ_W__SHIFT					6
-#define INST_SWIZ_W(x)						((x) << 6)
+#define INST_SWIZ_W(x)						(((x) << INST_SWIZ_W__SHIFT) & INST_SWIZ_W__MASK)
 #define VIV_ISA_WORD_0						0x00000000
 #define VIV_ISA_WORD_0_OPCODE__MASK				0x0000003f
 #define VIV_ISA_WORD_0_OPCODE__SHIFT				0
-#define VIV_ISA_WORD_0_OPCODE(x)				((x) << 0)
+#define VIV_ISA_WORD_0_OPCODE(x)				(((x) << VIV_ISA_WORD_0_OPCODE__SHIFT) & VIV_ISA_WORD_0_OPCODE__MASK)
 #define VIV_ISA_WORD_0_COND__MASK				0x000007c0
 #define VIV_ISA_WORD_0_COND__SHIFT				6
-#define VIV_ISA_WORD_0_COND(x)					((x) << 6)
+#define VIV_ISA_WORD_0_COND(x)					(((x) << VIV_ISA_WORD_0_COND__SHIFT) & VIV_ISA_WORD_0_COND__MASK)
 #define VIV_ISA_WORD_0_SAT					0x00000800
 #define VIV_ISA_WORD_0_DST_USE					0x00001000
 #define VIV_ISA_WORD_0_DST_AMODE__MASK				0x0000e000
 #define VIV_ISA_WORD_0_DST_AMODE__SHIFT				13
-#define VIV_ISA_WORD_0_DST_AMODE(x)				((x) << 13)
+#define VIV_ISA_WORD_0_DST_AMODE(x)				(((x) << VIV_ISA_WORD_0_DST_AMODE__SHIFT) & VIV_ISA_WORD_0_DST_AMODE__MASK)
 #define VIV_ISA_WORD_0_DST_REG__MASK				0x007f0000
 #define VIV_ISA_WORD_0_DST_REG__SHIFT				16
-#define VIV_ISA_WORD_0_DST_REG(x)				((x) << 16)
+#define VIV_ISA_WORD_0_DST_REG(x)				(((x) << VIV_ISA_WORD_0_DST_REG__SHIFT) & VIV_ISA_WORD_0_DST_REG__MASK)
 #define VIV_ISA_WORD_0_DST_COMPS__MASK				0x07800000
 #define VIV_ISA_WORD_0_DST_COMPS__SHIFT				23
-#define VIV_ISA_WORD_0_DST_COMPS(x)				((x) << 23)
+#define VIV_ISA_WORD_0_DST_COMPS(x)				(((x) << VIV_ISA_WORD_0_DST_COMPS__SHIFT) & VIV_ISA_WORD_0_DST_COMPS__MASK)
 #define VIV_ISA_WORD_0_TEX_ID__MASK				0xf8000000
 #define VIV_ISA_WORD_0_TEX_ID__SHIFT				27
-#define VIV_ISA_WORD_0_TEX_ID(x)				((x) << 27)
+#define VIV_ISA_WORD_0_TEX_ID(x)				(((x) << VIV_ISA_WORD_0_TEX_ID__SHIFT) & VIV_ISA_WORD_0_TEX_ID__MASK)
 
 #define VIV_ISA_WORD_1						0x00000004
 #define VIV_ISA_WORD_1_TEX_AMODE__MASK				0x00000007
 #define VIV_ISA_WORD_1_TEX_AMODE__SHIFT				0
-#define VIV_ISA_WORD_1_TEX_AMODE(x)				((x) << 0)
+#define VIV_ISA_WORD_1_TEX_AMODE(x)				(((x) << VIV_ISA_WORD_1_TEX_AMODE__SHIFT) & VIV_ISA_WORD_1_TEX_AMODE__MASK)
 #define VIV_ISA_WORD_1_TEX_SWIZ__MASK				0x000007f8
 #define VIV_ISA_WORD_1_TEX_SWIZ__SHIFT				3
-#define VIV_ISA_WORD_1_TEX_SWIZ(x)				((x) << 3)
+#define VIV_ISA_WORD_1_TEX_SWIZ(x)				(((x) << VIV_ISA_WORD_1_TEX_SWIZ__SHIFT) & VIV_ISA_WORD_1_TEX_SWIZ__MASK)
 #define VIV_ISA_WORD_1_SRC0_USE					0x00000800
 #define VIV_ISA_WORD_1_SRC0_REG__MASK				0x001ff000
 #define VIV_ISA_WORD_1_SRC0_REG__SHIFT				12
-#define VIV_ISA_WORD_1_SRC0_REG(x)				((x) << 12)
+#define VIV_ISA_WORD_1_SRC0_REG(x)				(((x) << VIV_ISA_WORD_1_SRC0_REG__SHIFT) & VIV_ISA_WORD_1_SRC0_REG__MASK)
 #define VIV_ISA_WORD_1_UNK1_21					0x00200000
 #define VIV_ISA_WORD_1_SRC0_SWIZ__MASK				0x3fc00000
 #define VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT				22
-#define VIV_ISA_WORD_1_SRC0_SWIZ(x)				((x) << 22)
+#define VIV_ISA_WORD_1_SRC0_SWIZ(x)				(((x) << VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT) & VIV_ISA_WORD_1_SRC0_SWIZ__MASK)
 #define VIV_ISA_WORD_1_SRC0_NEG					0x40000000
 #define VIV_ISA_WORD_1_SRC0_ABS					0x80000000
 
 #define VIV_ISA_WORD_2						0x00000008
 #define VIV_ISA_WORD_2_SRC0_AMODE__MASK				0x00000007
 #define VIV_ISA_WORD_2_SRC0_AMODE__SHIFT			0
-#define VIV_ISA_WORD_2_SRC0_AMODE(x)				((x) << 0)
+#define VIV_ISA_WORD_2_SRC0_AMODE(x)				(((x) << VIV_ISA_WORD_2_SRC0_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC0_AMODE__MASK)
 #define VIV_ISA_WORD_2_SRC0_RGROUP__MASK			0x00000038
 #define VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT			3
-#define VIV_ISA_WORD_2_SRC0_RGROUP(x)				((x) << 3)
+#define VIV_ISA_WORD_2_SRC0_RGROUP(x)				(((x) << VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT) & VIV_ISA_WORD_2_SRC0_RGROUP__MASK)
 #define VIV_ISA_WORD_2_SRC1_USE					0x00000040
 #define VIV_ISA_WORD_2_SRC1_REG__MASK				0x0000ff80
 #define VIV_ISA_WORD_2_SRC1_REG__SHIFT				7
-#define VIV_ISA_WORD_2_SRC1_REG(x)				((x) << 7)
+#define VIV_ISA_WORD_2_SRC1_REG(x)				(((x) << VIV_ISA_WORD_2_SRC1_REG__SHIFT) & VIV_ISA_WORD_2_SRC1_REG__MASK)
 #define VIV_ISA_WORD_2_UNK2_16					0x00010000
 #define VIV_ISA_WORD_2_SRC1_SWIZ__MASK				0x01fe0000
 #define VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT				17
-#define VIV_ISA_WORD_2_SRC1_SWIZ(x)				((x) << 17)
+#define VIV_ISA_WORD_2_SRC1_SWIZ(x)				(((x) << VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT) & VIV_ISA_WORD_2_SRC1_SWIZ__MASK)
 #define VIV_ISA_WORD_2_SRC1_NEG					0x02000000
 #define VIV_ISA_WORD_2_SRC1_ABS					0x04000000
 #define VIV_ISA_WORD_2_SRC1_AMODE__MASK				0x38000000
 #define VIV_ISA_WORD_2_SRC1_AMODE__SHIFT			27
-#define VIV_ISA_WORD_2_SRC1_AMODE(x)				((x) << 27)
+#define VIV_ISA_WORD_2_SRC1_AMODE(x)				(((x) << VIV_ISA_WORD_2_SRC1_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC1_AMODE__MASK)
 #define VIV_ISA_WORD_2_UNK2_30__MASK				0xc0000000
 #define VIV_ISA_WORD_2_UNK2_30__SHIFT				30
-#define VIV_ISA_WORD_2_UNK2_30(x)				((x) << 30)
+#define VIV_ISA_WORD_2_UNK2_30(x)				(((x) << VIV_ISA_WORD_2_UNK2_30__SHIFT) & VIV_ISA_WORD_2_UNK2_30__MASK)
 
 #define VIV_ISA_WORD_3						0x0000000c
 #define VIV_ISA_WORD_3_SRC1_RGROUP__MASK			0x00000007
 #define VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT			0
-#define VIV_ISA_WORD_3_SRC1_RGROUP(x)				((x) << 0)
+#define VIV_ISA_WORD_3_SRC1_RGROUP(x)				(((x) << VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC1_RGROUP__MASK)
 #define VIV_ISA_WORD_3_SRC2_IMM__MASK				0x003fff80
 #define VIV_ISA_WORD_3_SRC2_IMM__SHIFT				7
-#define VIV_ISA_WORD_3_SRC2_IMM(x)				((x) << 7)
+#define VIV_ISA_WORD_3_SRC2_IMM(x)				(((x) << VIV_ISA_WORD_3_SRC2_IMM__SHIFT) & VIV_ISA_WORD_3_SRC2_IMM__MASK)
 #define VIV_ISA_WORD_3_SRC2_USE					0x00000008
 #define VIV_ISA_WORD_3_SRC2_REG__MASK				0x00001ff0
 #define VIV_ISA_WORD_3_SRC2_REG__SHIFT				4
-#define VIV_ISA_WORD_3_SRC2_REG(x)				((x) << 4)
+#define VIV_ISA_WORD_3_SRC2_REG(x)				(((x) << VIV_ISA_WORD_3_SRC2_REG__SHIFT) & VIV_ISA_WORD_3_SRC2_REG__MASK)
 #define VIV_ISA_WORD_3_UNK3_13					0x00002000
 #define VIV_ISA_WORD_3_SRC2_SWIZ__MASK				0x003fc000
 #define VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT				14
-#define VIV_ISA_WORD_3_SRC2_SWIZ(x)				((x) << 14)
+#define VIV_ISA_WORD_3_SRC2_SWIZ(x)				(((x) << VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT) & VIV_ISA_WORD_3_SRC2_SWIZ__MASK)
 #define VIV_ISA_WORD_3_SRC2_NEG					0x00400000
 #define VIV_ISA_WORD_3_SRC2_ABS					0x00800000
 #define VIV_ISA_WORD_3_UNK3_24					0x01000000
 #define VIV_ISA_WORD_3_SRC2_AMODE__MASK				0x0e000000
 #define VIV_ISA_WORD_3_SRC2_AMODE__SHIFT			25
-#define VIV_ISA_WORD_3_SRC2_AMODE(x)				((x) << 25)
+#define VIV_ISA_WORD_3_SRC2_AMODE(x)				(((x) << VIV_ISA_WORD_3_SRC2_AMODE__SHIFT) & VIV_ISA_WORD_3_SRC2_AMODE__MASK)
 #define VIV_ISA_WORD_3_SRC2_RGROUP__MASK			0x70000000
 #define VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT			28
-#define VIV_ISA_WORD_3_SRC2_RGROUP(x)				((x) << 28)
+#define VIV_ISA_WORD_3_SRC2_RGROUP(x)				(((x) << VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC2_RGROUP__MASK)
 #define VIV_ISA_WORD_3_UNK3_31					0x80000000
 
 
diff --git a/native/include/etna/state.xml.h b/native/include/etna/state.xml.h
index aec629c..f06ecb7 100644
--- a/native/include/etna/state.xml.h
+++ b/native/include/etna/state.xml.h
@@ -8,7 +8,7 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- /home/orion/projects/etna_viv/rnndb/state.xml ( 111874 bytes, from 2013-01-21 07:20:03)
+- /home/orion/projects/etna_viv/rnndb/state.xml ( 113930 bytes, from 2013-01-23 21:08:41)
 
 Copyright (C) 2013
 */
@@ -350,16 +350,16 @@ Copyright (C) 2013
 #define RGBA_BITS_A						0x00000008
 #define DE_COLOR_BLUE__MASK					0x000000ff
 #define DE_COLOR_BLUE__SHIFT					0
-#define DE_COLOR_BLUE(x)					((x) << 0)
+#define DE_COLOR_BLUE(x)					(((x) << DE_COLOR_BLUE__SHIFT) & DE_COLOR_BLUE__MASK)
 #define DE_COLOR_GREEN__MASK					0x0000ff00
 #define DE_COLOR_GREEN__SHIFT					8
-#define DE_COLOR_GREEN(x)					((x) << 8)
+#define DE_COLOR_GREEN(x)					(((x) << DE_COLOR_GREEN__SHIFT) & DE_COLOR_GREEN__MASK)
 #define DE_COLOR_RED__MASK					0x00ff0000
 #define DE_COLOR_RED__SHIFT					16
-#define DE_COLOR_RED(x)						((x) << 16)
+#define DE_COLOR_RED(x)						(((x) << DE_COLOR_RED__SHIFT) & DE_COLOR_RED__MASK)
 #define DE_COLOR_ALPHA__MASK					0xff000000
 #define DE_COLOR_ALPHA__SHIFT					24
-#define DE_COLOR_ALPHA(x)					((x) << 24)
+#define DE_COLOR_ALPHA(x)					(((x) << DE_COLOR_ALPHA__SHIFT) & DE_COLOR_ALPHA__MASK)
 #define VIVS_HI							0x00000000
 
 #define VIVS_HI_CLOCK_CONTROL					0x00000000
@@ -367,7 +367,7 @@ Copyright (C) 2013
 #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS				0x00000002
 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK			0x000001fc
 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT			2
-#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x)			((x) << 2)
+#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x)			(((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK)
 #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD			0x00000200
 #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING		0x00000400
 #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS		0x00000800
@@ -395,36 +395,36 @@ Copyright (C) 2013
 #define VIVS_HI_AXI_CONFIG					0x00000008
 #define VIVS_HI_AXI_CONFIG_AWID__MASK				0x0000000f
 #define VIVS_HI_AXI_CONFIG_AWID__SHIFT				0
-#define VIVS_HI_AXI_CONFIG_AWID(x)				((x) << 0)
+#define VIVS_HI_AXI_CONFIG_AWID(x)				(((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK)
 #define VIVS_HI_AXI_CONFIG_ARID__MASK				0x000000f0
 #define VIVS_HI_AXI_CONFIG_ARID__SHIFT				4
-#define VIVS_HI_AXI_CONFIG_ARID(x)				((x) << 4)
+#define VIVS_HI_AXI_CONFIG_ARID(x)				(((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK)
 #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK			0x00000f00
 #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT			8
-#define VIVS_HI_AXI_CONFIG_AWCACHE(x)				((x) << 8)
+#define VIVS_HI_AXI_CONFIG_AWCACHE(x)				(((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK)
 #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK			0x0000f000
 #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT			12
-#define VIVS_HI_AXI_CONFIG_ARCACHE(x)				((x) << 12)
+#define VIVS_HI_AXI_CONFIG_ARCACHE(x)				(((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK)
 
 #define VIVS_HI_AXI_STATUS					0x0000000c
 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK			0x0000000f
 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT			0
-#define VIVS_HI_AXI_STATUS_WR_ERR_ID(x)				((x) << 0)
+#define VIVS_HI_AXI_STATUS_WR_ERR_ID(x)				(((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK)
 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK			0x000000f0
 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT			4
-#define VIVS_HI_AXI_STATUS_RD_ERR_ID(x)				((x) << 4)
+#define VIVS_HI_AXI_STATUS_RD_ERR_ID(x)				(((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK)
 #define VIVS_HI_AXI_STATUS_DET_WR_ERR				0x00000100
 #define VIVS_HI_AXI_STATUS_DET_RD_ERR				0x00000200
 
 #define VIVS_HI_INTR_ACKNOWLEDGE				0x00000010
 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK			0xffffffff
 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT		0
-#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x)			((x) << 0)
+#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x)			(((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)
 
 #define VIVS_HI_INTR_ENBL					0x00000014
 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK			0xffffffff
 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT			0
-#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x)			((x) << 0)
+#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x)			(((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK)
 
 #define VIVS_HI_CHIP_IDENTITY					0x00000018
 
@@ -507,21 +507,21 @@ Copyright (C) 2013
 #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK			0x00000100
 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK			0xfffffc00
 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT			10
-#define VIVS_MMUv2_CONFIGURATION_ADDRESS(x)			((x) << 10)
+#define VIVS_MMUv2_CONFIGURATION_ADDRESS(x)			(((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK)
 
 #define VIVS_MMUv2_STATUS					0x00000188
 #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK			0x00000003
 #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT			0
-#define VIVS_MMUv2_STATUS_EXCEPTION0(x)				((x) << 0)
+#define VIVS_MMUv2_STATUS_EXCEPTION0(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK)
 #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK			0x00000030
 #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT			4
-#define VIVS_MMUv2_STATUS_EXCEPTION1(x)				((x) << 4)
+#define VIVS_MMUv2_STATUS_EXCEPTION1(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK)
 #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK			0x00000300
 #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT			8
-#define VIVS_MMUv2_STATUS_EXCEPTION2(x)				((x) << 8)
+#define VIVS_MMUv2_STATUS_EXCEPTION2(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK)
 #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK			0x00003000
 #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT			12
-#define VIVS_MMUv2_STATUS_EXCEPTION3(x)				((x) << 12)
+#define VIVS_MMUv2_STATUS_EXCEPTION3(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK)
 
 #define VIVS_MMUv2_CONTROL					0x0000018c
 #define VIVS_MMUv2_CONTROL_ENABLE				0x00000001
@@ -614,11 +614,11 @@ Copyright (C) 2013
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT_10_10_10_2	0x0000000d
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK		0x00000030
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT		4
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x)			((x) << 4)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE		0x00000080
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK		0x00000700
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT		8
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x)			((x) << 8)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK			0x00003000
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT		12
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM_4			0x00000000
@@ -631,10 +631,10 @@ Copyright (C) 2013
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON		0x00008000
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK		0x00ff0000
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT		16
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x)			((x) << 16)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK			0xff000000
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT		24
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x)			((x) << 24)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)
 
 #define VIVS_FE_CMD_STREAM_BASE_ADDR				0x00000640
 
@@ -652,14 +652,14 @@ Copyright (C) 2013
 #define VIVS_FE_VERTEX_STREAM_CONTROL				0x00000650
 #define VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK	0x000000ff
 #define VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT	0
-#define VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x)		((x) << 0)
+#define VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x)		(((x) << VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & VIVS_FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
 
 #define VIVS_FE_COMMAND_ADDRESS					0x00000654
 
 #define VIVS_FE_COMMAND_CONTROL					0x00000658
 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK			0x0000ffff
 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT			0
-#define VIVS_FE_COMMAND_CONTROL_PREFETCH(x)			((x) << 0)
+#define VIVS_FE_COMMAND_CONTROL_PREFETCH(x)			(((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)
 #define VIVS_FE_COMMAND_CONTROL_ENABLE				0x00010000
 
 #define VIVS_FE_DMA_STATUS					0x0000065c
@@ -667,22 +667,22 @@ Copyright (C) 2013
 #define VIVS_FE_DMA_DEBUG_STATE					0x00000660
 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK			0x0000001f
 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT		0
-#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE(x)			((x) << 0)
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE(x)			(((x) << VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT) & VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK)
 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK		0x00000300
 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT		8
-#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE(x)		((x) << 8)
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE(x)		(((x) << VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT) & VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK)
 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK		0x00000c00
 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT		10
-#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE(x)		((x) << 10)
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE(x)		(((x) << VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT) & VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK)
 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK		0x00003000
 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT		12
-#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE(x)		((x) << 12)
+#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE(x)		(((x) << VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT) & VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK)
 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK			0x0000c000
 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT		14
-#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE(x)			((x) << 14)
+#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE(x)			(((x) << VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT) & VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK)
 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK		0x00030000
 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT		16
-#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE(x)			((x) << 16)
+#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE(x)			(((x) << VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT) & VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK)
 
 #define VIVS_FE_DMA_ADDRESS					0x00000664
 
@@ -721,22 +721,22 @@ Copyright (C) 2013
 #define VIVS_GL_PIPE_SELECT					0x00003800
 #define VIVS_GL_PIPE_SELECT_PIPE__MASK				0x00000001
 #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT				0
-#define VIVS_GL_PIPE_SELECT_PIPE(x)				((x) << 0)
+#define VIVS_GL_PIPE_SELECT_PIPE(x)				(((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)
 
 #define VIVS_GL_EVENT						0x00003804
 #define VIVS_GL_EVENT_EVENT_ID__MASK				0x0000001f
 #define VIVS_GL_EVENT_EVENT_ID__SHIFT				0
-#define VIVS_GL_EVENT_EVENT_ID(x)				((x) << 0)
+#define VIVS_GL_EVENT_EVENT_ID(x)				(((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
 #define VIVS_GL_EVENT_FROM_FE					0x00000020
 #define VIVS_GL_EVENT_FROM_PE					0x00000040
 
 #define VIVS_GL_SEMAPHORE_TOKEN					0x00003808
 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK			0x0000001f
 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT			0
-#define VIVS_GL_SEMAPHORE_TOKEN_FROM(x)				((x) << 0)
+#define VIVS_GL_SEMAPHORE_TOKEN_FROM(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)
 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK			0x00001f00
 #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT			8
-#define VIVS_GL_SEMAPHORE_TOKEN_TO(x)				((x) << 8)
+#define VIVS_GL_SEMAPHORE_TOKEN_TO(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
 
 #define VIVS_GL_FLUSH_CACHE					0x0000380c
 #define VIVS_GL_FLUSH_CACHE_DEPTH				0x00000001
@@ -761,99 +761,99 @@ Copyright (C) 2013
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK		0x00000008
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK		0x000000f0
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT		4
-#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x)		((x) << 4)
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x)		(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK		0x00000100
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK			0x00007000
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT		12
-#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x)			((x) << 12)
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK			0x00008000
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK			0x00030000
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT		16
-#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x)			((x) << 16)
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)
 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK			0x00080000
 
 #define VIVS_GL_VARYING_TOTAL_COMPONENTS			0x0000381c
 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK		0x000000ff
 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT		0
-#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x)			((x) << 0)
+#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x)			(((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
 
 #define VIVS_GL_VARYING_NUM_COMPONENTS				0x00003820
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK		0x00000007
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT		0
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(x)			((x) << 0)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK		0x00000070
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT		4
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(x)			((x) << 4)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK		0x00000700
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT		8
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2(x)			((x) << 8)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK		0x00007000
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT		12
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3(x)			((x) << 12)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK		0x00070000
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT		16
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4(x)			((x) << 16)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK		0x00700000
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT		20
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5(x)			((x) << 20)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK		0x07000000
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT		24
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6(x)			((x) << 24)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK		0x70000000
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT		28
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x)			((x) << 28)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK)
 
 #define VIVS_GL_VARYING_COMPONENT_USE(i0)		       (0x00003828 + 0x4*(i0))
 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE			0x00000004
 #define VIVS_GL_VARYING_COMPONENT_USE__LEN			0x00000002
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK		0x00000003
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT		0
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x)			((x) << 0)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK		0x0000000c
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT		2
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x)			((x) << 2)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK		0x00000030
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT		4
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x)			((x) << 4)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK		0x000000c0
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT		6
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x)			((x) << 6)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK		0x00000300
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT		8
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x)			((x) << 8)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK		0x00000c00
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT		10
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x)			((x) << 10)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK		0x00003000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT		12
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x)			((x) << 12)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK		0x0000c000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT		14
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x)			((x) << 14)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK		0x00030000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT		16
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x)			((x) << 16)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK		0x000c0000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT		18
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x)			((x) << 18)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK		0x00300000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT		20
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x)			((x) << 20)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK		0x00c00000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT		22
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x)			((x) << 22)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK		0x03000000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT		24
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x)			((x) << 24)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK		0x0c000000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT		26
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x)			((x) << 26)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK		0x30000000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT		28
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x)			((x) << 28)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK		0xc0000000
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT		30
-#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)			((x) << 30)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
 
 #define VIVS_GL_UNK03834					0x00003834
 
@@ -871,10 +871,10 @@ Copyright (C) 2013
 #define VIVS_GL_STALL_TOKEN					0x00003c00
 #define VIVS_GL_STALL_TOKEN_FROM__MASK				0x0000001f
 #define VIVS_GL_STALL_TOKEN_FROM__SHIFT				0
-#define VIVS_GL_STALL_TOKEN_FROM(x)				((x) << 0)
+#define VIVS_GL_STALL_TOKEN_FROM(x)				(((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)
 #define VIVS_GL_STALL_TOKEN_TO__MASK				0x00001f00
 #define VIVS_GL_STALL_TOKEN_TO__SHIFT				8
-#define VIVS_GL_STALL_TOKEN_TO(x)				((x) << 8)
+#define VIVS_GL_STALL_TOKEN_TO(x)				(((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)
 #define VIVS_GL_STALL_TOKEN_FLIP0				0x40000000
 #define VIVS_GL_STALL_TOKEN_FLIP1				0x80000000
 
@@ -885,12 +885,12 @@ Copyright (C) 2013
 #define VIVS_DE_SRC_STRIDE					0x00001204
 #define VIVS_DE_SRC_STRIDE_STRIDE__MASK				0x0003ffff
 #define VIVS_DE_SRC_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_SRC_STRIDE_STRIDE(x)				((x) << 0)
+#define VIVS_DE_SRC_STRIDE_STRIDE(x)				(((x) << VIVS_DE_SRC_STRIDE_STRIDE__SHIFT) & VIVS_DE_SRC_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_SRC_ROTATION_CONFIG				0x00001208
 #define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__MASK			0x0000ffff
 #define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__SHIFT		0
-#define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH(x)			((x) << 0)
+#define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH(x)			(((x) << VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__MASK)
 #define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION__MASK		0x00010000
 #define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION__SHIFT		16
 #define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION_DISABLE		0x00000000
@@ -921,33 +921,33 @@ Copyright (C) 2013
 #define VIVS_DE_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND		0x00008000
 #define VIVS_DE_SRC_CONFIG_SWIZZLE__MASK			0x00300000
 #define VIVS_DE_SRC_CONFIG_SWIZZLE__SHIFT			20
-#define VIVS_DE_SRC_CONFIG_SWIZZLE(x)				((x) << 20)
+#define VIVS_DE_SRC_CONFIG_SWIZZLE(x)				(((x) << VIVS_DE_SRC_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_SRC_CONFIG_SWIZZLE__MASK)
 #define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__MASK			0x1f000000
 #define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__SHIFT			24
-#define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT(x)			((x) << 24)
+#define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT(x)			(((x) << VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__MASK)
 #define VIVS_DE_SRC_CONFIG_DISABLE420_L2_CACHE__MASK		0x20000000
 #define VIVS_DE_SRC_CONFIG_DISABLE420_L2_CACHE__SHIFT		29
 #define VIVS_DE_SRC_CONFIG_DISABLE420_L2_CACHE_DISABLE		0x00000000
 #define VIVS_DE_SRC_CONFIG_DISABLE420_L2_CACHE_ENABLE		0x20000000
 #define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__MASK			0xc0000000
 #define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__SHIFT		30
-#define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL(x)			((x) << 30)
+#define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL(x)			(((x) << VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__MASK)
 
 #define VIVS_DE_SRC_ORIGIN					0x00001210
 #define VIVS_DE_SRC_ORIGIN_X__MASK				0x0000ffff
 #define VIVS_DE_SRC_ORIGIN_X__SHIFT				0
-#define VIVS_DE_SRC_ORIGIN_X(x)					((x) << 0)
+#define VIVS_DE_SRC_ORIGIN_X(x)					(((x) << VIVS_DE_SRC_ORIGIN_X__SHIFT) & VIVS_DE_SRC_ORIGIN_X__MASK)
 #define VIVS_DE_SRC_ORIGIN_Y__MASK				0xffff0000
 #define VIVS_DE_SRC_ORIGIN_Y__SHIFT				16
-#define VIVS_DE_SRC_ORIGIN_Y(x)					((x) << 16)
+#define VIVS_DE_SRC_ORIGIN_Y(x)					(((x) << VIVS_DE_SRC_ORIGIN_Y__SHIFT) & VIVS_DE_SRC_ORIGIN_Y__MASK)
 
 #define VIVS_DE_SRC_SIZE					0x00001214
 #define VIVS_DE_SRC_SIZE_X__MASK				0x0000ffff
 #define VIVS_DE_SRC_SIZE_X__SHIFT				0
-#define VIVS_DE_SRC_SIZE_X(x)					((x) << 0)
+#define VIVS_DE_SRC_SIZE_X(x)					(((x) << VIVS_DE_SRC_SIZE_X__SHIFT) & VIVS_DE_SRC_SIZE_X__MASK)
 #define VIVS_DE_SRC_SIZE_Y__MASK				0xffff0000
 #define VIVS_DE_SRC_SIZE_Y__SHIFT				16
-#define VIVS_DE_SRC_SIZE_Y(x)					((x) << 16)
+#define VIVS_DE_SRC_SIZE_Y(x)					(((x) << VIVS_DE_SRC_SIZE_Y__SHIFT) & VIVS_DE_SRC_SIZE_Y__MASK)
 
 #define VIVS_DE_SRC_COLOR_BG					0x00001218
 
@@ -956,24 +956,24 @@ Copyright (C) 2013
 #define VIVS_DE_STRETCH_FACTOR_LOW				0x00001220
 #define VIVS_DE_STRETCH_FACTOR_LOW_X__MASK			0x7fffffff
 #define VIVS_DE_STRETCH_FACTOR_LOW_X__SHIFT			0
-#define VIVS_DE_STRETCH_FACTOR_LOW_X(x)				((x) << 0)
+#define VIVS_DE_STRETCH_FACTOR_LOW_X(x)				(((x) << VIVS_DE_STRETCH_FACTOR_LOW_X__SHIFT) & VIVS_DE_STRETCH_FACTOR_LOW_X__MASK)
 
 #define VIVS_DE_STRETCH_FACTOR_HIGH				0x00001224
 #define VIVS_DE_STRETCH_FACTOR_HIGH_Y__MASK			0x7fffffff
 #define VIVS_DE_STRETCH_FACTOR_HIGH_Y__SHIFT			0
-#define VIVS_DE_STRETCH_FACTOR_HIGH_Y(x)			((x) << 0)
+#define VIVS_DE_STRETCH_FACTOR_HIGH_Y(x)			(((x) << VIVS_DE_STRETCH_FACTOR_HIGH_Y__SHIFT) & VIVS_DE_STRETCH_FACTOR_HIGH_Y__MASK)
 
 #define VIVS_DE_DEST_ADDRESS					0x00001228
 
 #define VIVS_DE_DEST_STRIDE					0x0000122c
 #define VIVS_DE_DEST_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_DEST_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_DEST_STRIDE_STRIDE(x)				((x) << 0)
+#define VIVS_DE_DEST_STRIDE_STRIDE(x)				(((x) << VIVS_DE_DEST_STRIDE_STRIDE__SHIFT) & VIVS_DE_DEST_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_DEST_ROTATION_CONFIG				0x00001230
 #define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__MASK		0x0000ffff
 #define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__SHIFT		0
-#define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH(x)			((x) << 0)
+#define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH(x)			(((x) << VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__MASK)
 #define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION__MASK		0x00010000
 #define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION__SHIFT		16
 #define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION_DISABLE		0x00000000
@@ -982,7 +982,7 @@ Copyright (C) 2013
 #define VIVS_DE_DEST_CONFIG					0x00001234
 #define VIVS_DE_DEST_CONFIG_FORMAT__MASK			0x0000001f
 #define VIVS_DE_DEST_CONFIG_FORMAT__SHIFT			0
-#define VIVS_DE_DEST_CONFIG_FORMAT(x)				((x) << 0)
+#define VIVS_DE_DEST_CONFIG_FORMAT(x)				(((x) << VIVS_DE_DEST_CONFIG_FORMAT__SHIFT) & VIVS_DE_DEST_CONFIG_FORMAT__MASK)
 #define VIVS_DE_DEST_CONFIG_TILED__MASK				0x00000100
 #define VIVS_DE_DEST_CONFIG_TILED__SHIFT			8
 #define VIVS_DE_DEST_CONFIG_TILED_DISABLE			0x00000000
@@ -1000,10 +1000,10 @@ Copyright (C) 2013
 #define VIVS_DE_DEST_CONFIG_COMMAND_MULTI_SOURCE_BLT		0x00008000
 #define VIVS_DE_DEST_CONFIG_SWIZZLE__MASK			0x00030000
 #define VIVS_DE_DEST_CONFIG_SWIZZLE__SHIFT			16
-#define VIVS_DE_DEST_CONFIG_SWIZZLE(x)				((x) << 16)
+#define VIVS_DE_DEST_CONFIG_SWIZZLE(x)				(((x) << VIVS_DE_DEST_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_DEST_CONFIG_SWIZZLE__MASK)
 #define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__MASK		0x00300000
 #define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__SHIFT		20
-#define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL(x)			((x) << 20)
+#define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL(x)			(((x) << VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__MASK)
 #define VIVS_DE_DEST_CONFIG_GDI_STRE__MASK			0x01000000
 #define VIVS_DE_DEST_CONFIG_GDI_STRE__SHIFT			24
 #define VIVS_DE_DEST_CONFIG_GDI_STRE_DISABLE			0x00000000
@@ -1020,10 +1020,10 @@ Copyright (C) 2013
 #define VIVS_DE_ROP						0x0000125c
 #define VIVS_DE_ROP_ROP_FG__MASK				0x000000ff
 #define VIVS_DE_ROP_ROP_FG__SHIFT				0
-#define VIVS_DE_ROP_ROP_FG(x)					((x) << 0)
+#define VIVS_DE_ROP_ROP_FG(x)					(((x) << VIVS_DE_ROP_ROP_FG__SHIFT) & VIVS_DE_ROP_ROP_FG__MASK)
 #define VIVS_DE_ROP_ROP_BG__MASK				0x0000ff00
 #define VIVS_DE_ROP_ROP_BG__SHIFT				8
-#define VIVS_DE_ROP_ROP_BG(x)					((x) << 8)
+#define VIVS_DE_ROP_ROP_BG(x)					(((x) << VIVS_DE_ROP_ROP_BG__SHIFT) & VIVS_DE_ROP_ROP_BG__MASK)
 #define VIVS_DE_ROP_TYPE__MASK					0x00300000
 #define VIVS_DE_ROP_TYPE__SHIFT					20
 #define VIVS_DE_ROP_TYPE_ROP2_PATTERN				0x00000000
@@ -1034,18 +1034,18 @@ Copyright (C) 2013
 #define VIVS_DE_CLIP_TOP_LEFT					0x00001260
 #define VIVS_DE_CLIP_TOP_LEFT_X__MASK				0x00007fff
 #define VIVS_DE_CLIP_TOP_LEFT_X__SHIFT				0
-#define VIVS_DE_CLIP_TOP_LEFT_X(x)				((x) << 0)
+#define VIVS_DE_CLIP_TOP_LEFT_X(x)				(((x) << VIVS_DE_CLIP_TOP_LEFT_X__SHIFT) & VIVS_DE_CLIP_TOP_LEFT_X__MASK)
 #define VIVS_DE_CLIP_TOP_LEFT_Y__MASK				0x7fff0000
 #define VIVS_DE_CLIP_TOP_LEFT_Y__SHIFT				16
-#define VIVS_DE_CLIP_TOP_LEFT_Y(x)				((x) << 16)
+#define VIVS_DE_CLIP_TOP_LEFT_Y(x)				(((x) << VIVS_DE_CLIP_TOP_LEFT_Y__SHIFT) & VIVS_DE_CLIP_TOP_LEFT_Y__MASK)
 
 #define VIVS_DE_CLIP_BOTTOM_RIGHT				0x00001264
 #define VIVS_DE_CLIP_BOTTOM_RIGHT_X__MASK			0x00007fff
 #define VIVS_DE_CLIP_BOTTOM_RIGHT_X__SHIFT			0
-#define VIVS_DE_CLIP_BOTTOM_RIGHT_X(x)				((x) << 0)
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_X(x)				(((x) << VIVS_DE_CLIP_BOTTOM_RIGHT_X__SHIFT) & VIVS_DE_CLIP_BOTTOM_RIGHT_X__MASK)
 #define VIVS_DE_CLIP_BOTTOM_RIGHT_Y__MASK			0x7fff0000
 #define VIVS_DE_CLIP_BOTTOM_RIGHT_Y__SHIFT			16
-#define VIVS_DE_CLIP_BOTTOM_RIGHT_Y(x)				((x) << 16)
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_Y(x)				(((x) << VIVS_DE_CLIP_BOTTOM_RIGHT_Y__SHIFT) & VIVS_DE_CLIP_BOTTOM_RIGHT_Y__MASK)
 
 #define VIVS_DE_CONFIG						0x0000126c
 #define VIVS_DE_CONFIG_MIRROR_BLT_ENABLE__MASK			0x00000001
@@ -1060,18 +1060,18 @@ Copyright (C) 2013
 #define VIVS_DE_CONFIG_MIRROR_BLT_MODE_FULL_MIRROR		0x00000030
 #define VIVS_DE_CONFIG_SOURCE_SELECT__MASK			0x00070000
 #define VIVS_DE_CONFIG_SOURCE_SELECT__SHIFT			16
-#define VIVS_DE_CONFIG_SOURCE_SELECT(x)				((x) << 16)
+#define VIVS_DE_CONFIG_SOURCE_SELECT(x)				(((x) << VIVS_DE_CONFIG_SOURCE_SELECT__SHIFT) & VIVS_DE_CONFIG_SOURCE_SELECT__MASK)
 #define VIVS_DE_CONFIG_DESTINATION_SELECT__MASK			0x00300000
 #define VIVS_DE_CONFIG_DESTINATION_SELECT__SHIFT		20
-#define VIVS_DE_CONFIG_DESTINATION_SELECT(x)			((x) << 20)
+#define VIVS_DE_CONFIG_DESTINATION_SELECT(x)			(((x) << VIVS_DE_CONFIG_DESTINATION_SELECT__SHIFT) & VIVS_DE_CONFIG_DESTINATION_SELECT__MASK)
 
 #define VIVS_DE_SRC_ORIGIN_FRACTION				0x00001278
 #define VIVS_DE_SRC_ORIGIN_FRACTION_X__MASK			0x0000ffff
 #define VIVS_DE_SRC_ORIGIN_FRACTION_X__SHIFT			0
-#define VIVS_DE_SRC_ORIGIN_FRACTION_X(x)			((x) << 0)
+#define VIVS_DE_SRC_ORIGIN_FRACTION_X(x)			(((x) << VIVS_DE_SRC_ORIGIN_FRACTION_X__SHIFT) & VIVS_DE_SRC_ORIGIN_FRACTION_X__MASK)
 #define VIVS_DE_SRC_ORIGIN_FRACTION_Y__MASK			0xffff0000
 #define VIVS_DE_SRC_ORIGIN_FRACTION_Y__SHIFT			16
-#define VIVS_DE_SRC_ORIGIN_FRACTION_Y(x)			((x) << 16)
+#define VIVS_DE_SRC_ORIGIN_FRACTION_Y(x)			(((x) << VIVS_DE_SRC_ORIGIN_FRACTION_Y__SHIFT) & VIVS_DE_SRC_ORIGIN_FRACTION_Y__MASK)
 
 #define VIVS_DE_ALPHA_CONTROL					0x0000127c
 #define VIVS_DE_ALPHA_CONTROL_ENABLE__MASK			0x00000001
@@ -1100,14 +1100,14 @@ Copyright (C) 2013
 #define VIVS_DE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED	0x00002000
 #define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__MASK		0x07000000
 #define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT		24
-#define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE(x)		((x) << 24)
+#define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE(x)		(((x) << VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT) & VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__MASK)
 #define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR__MASK		0x08000000
 #define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR__SHIFT		27
 #define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLE		0x00000000
 #define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLE		0x08000000
 #define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__MASK		0x70000000
 #define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__SHIFT		28
-#define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE(x)		((x) << 28)
+#define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE(x)		(((x) << VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__SHIFT) & VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__MASK)
 #define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR__MASK		0x80000000
 #define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR__SHIFT		31
 #define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLE		0x00000000
@@ -1118,14 +1118,14 @@ Copyright (C) 2013
 #define VIVS_DE_UPLANE_STRIDE					0x00001288
 #define VIVS_DE_UPLANE_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_UPLANE_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_UPLANE_STRIDE_STRIDE(x)				((x) << 0)
+#define VIVS_DE_UPLANE_STRIDE_STRIDE(x)				(((x) << VIVS_DE_UPLANE_STRIDE_STRIDE__SHIFT) & VIVS_DE_UPLANE_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_VPLANE_ADDRESS					0x0000128c
 
 #define VIVS_DE_VPLANE_STRIDE					0x00001290
 #define VIVS_DE_VPLANE_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_VPLANE_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_VPLANE_STRIDE_STRIDE(x)				((x) << 0)
+#define VIVS_DE_VPLANE_STRIDE_STRIDE(x)				(((x) << VIVS_DE_VPLANE_STRIDE_STRIDE__SHIFT) & VIVS_DE_VPLANE_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_VR_CONFIG					0x00001294
 #define VIVS_DE_VR_CONFIG_START__MASK				0x00000003
@@ -1138,44 +1138,44 @@ Copyright (C) 2013
 #define VIVS_DE_VR_SOURCE_IMAGE_LOW				0x00001298
 #define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__MASK			0x0000ffff
 #define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__SHIFT			0
-#define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT(x)			((x) << 0)
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__MASK)
 #define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__MASK			0xffff0000
 #define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__SHIFT			16
-#define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP(x)			((x) << 16)
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__MASK)
 
 #define VIVS_DE_VR_SOURCE_IMAGE_HIGH				0x0000129c
 #define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__MASK		0x0000ffff
 #define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__SHIFT		0
-#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT(x)			((x) << 0)
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__MASK)
 #define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__MASK		0xffff0000
 #define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__SHIFT		16
-#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM(x)			((x) << 16)
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__MASK)
 
 #define VIVS_DE_VR_SOURCE_ORIGIN_LOW				0x000012a0
 #define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__MASK			0xffffffff
 #define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__SHIFT			0
-#define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X(x)			((x) << 0)
+#define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X(x)			(((x) << VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__SHIFT) & VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__MASK)
 
 #define VIVS_DE_VR_SOURCE_ORIGIN_HIGH				0x000012a4
 #define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__MASK			0xffffffff
 #define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__SHIFT			0
-#define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y(x)			((x) << 0)
+#define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y(x)			(((x) << VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__SHIFT) & VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__MASK)
 
 #define VIVS_DE_VR_TARGET_WINDOW_LOW				0x000012a8
 #define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__MASK			0x0000ffff
 #define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__SHIFT		0
-#define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT(x)			((x) << 0)
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__MASK)
 #define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__MASK			0xffff0000
 #define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__SHIFT			16
-#define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP(x)			((x) << 16)
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__MASK)
 
 #define VIVS_DE_VR_TARGET_WINDOW_HIGH				0x000012ac
 #define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__MASK		0x0000ffff
 #define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__SHIFT		0
-#define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT(x)			((x) << 0)
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__MASK)
 #define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__MASK		0xffff0000
 #define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__SHIFT		16
-#define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM(x)			((x) << 16)
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__MASK)
 
 #define VIVS_DE_PE_CONFIG					0x000012b0
 #define VIVS_DE_PE_CONFIG_DESTINATION_FETCH__MASK		0x00000003
@@ -1188,29 +1188,29 @@ Copyright (C) 2013
 #define VIVS_DE_DST_ROTATION_HEIGHT				0x000012b4
 #define VIVS_DE_DST_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
 #define VIVS_DE_DST_ROTATION_HEIGHT_HEIGHT__SHIFT		0
-#define VIVS_DE_DST_ROTATION_HEIGHT_HEIGHT(x)			((x) << 0)
+#define VIVS_DE_DST_ROTATION_HEIGHT_HEIGHT(x)			(((x) << VIVS_DE_DST_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_DST_ROTATION_HEIGHT_HEIGHT__MASK)
 
 #define VIVS_DE_SRC_ROTATION_HEIGHT				0x000012b8
 #define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
 #define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT		0
-#define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT(x)			((x) << 0)
+#define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT(x)			(((x) << VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__MASK)
 
 #define VIVS_DE_ROT_ANGLE					0x000012bc
 #define VIVS_DE_ROT_ANGLE_SRC__MASK				0x00000007
 #define VIVS_DE_ROT_ANGLE_SRC__SHIFT				0
-#define VIVS_DE_ROT_ANGLE_SRC(x)				((x) << 0)
+#define VIVS_DE_ROT_ANGLE_SRC(x)				(((x) << VIVS_DE_ROT_ANGLE_SRC__SHIFT) & VIVS_DE_ROT_ANGLE_SRC__MASK)
 #define VIVS_DE_ROT_ANGLE_DST__MASK				0x00000038
 #define VIVS_DE_ROT_ANGLE_DST__SHIFT				3
-#define VIVS_DE_ROT_ANGLE_DST(x)				((x) << 3)
+#define VIVS_DE_ROT_ANGLE_DST(x)				(((x) << VIVS_DE_ROT_ANGLE_DST__SHIFT) & VIVS_DE_ROT_ANGLE_DST__MASK)
 #define VIVS_DE_ROT_ANGLE_SRC_MASK				0x00000100
 #define VIVS_DE_ROT_ANGLE_DST_MASK				0x00000200
 #define VIVS_DE_ROT_ANGLE_SRC_MIRROR__MASK			0x00003000
 #define VIVS_DE_ROT_ANGLE_SRC_MIRROR__SHIFT			12
-#define VIVS_DE_ROT_ANGLE_SRC_MIRROR(x)				((x) << 12)
+#define VIVS_DE_ROT_ANGLE_SRC_MIRROR(x)				(((x) << VIVS_DE_ROT_ANGLE_SRC_MIRROR__SHIFT) & VIVS_DE_ROT_ANGLE_SRC_MIRROR__MASK)
 #define VIVS_DE_ROT_ANGLE_SRC_MIRROR_MASK			0x00008000
 #define VIVS_DE_ROT_ANGLE_DST_MIRROR__MASK			0x00030000
 #define VIVS_DE_ROT_ANGLE_DST_MIRROR__SHIFT			16
-#define VIVS_DE_ROT_ANGLE_DST_MIRROR(x)				((x) << 16)
+#define VIVS_DE_ROT_ANGLE_DST_MIRROR(x)				(((x) << VIVS_DE_ROT_ANGLE_DST_MIRROR__SHIFT) & VIVS_DE_ROT_ANGLE_DST_MIRROR__MASK)
 #define VIVS_DE_ROT_ANGLE_DST_MIRROR_MASK			0x00080000
 
 #define VIVS_DE_CLEAR_PIXEL_VALUE32				0x000012c0
@@ -1309,60 +1309,60 @@ Copyright (C) 2013
 #define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_MASK		0x00000008
 #define VIVS_DE_VR_CONFIG_EX_FILTER_TAP__MASK			0x000000f0
 #define VIVS_DE_VR_CONFIG_EX_FILTER_TAP__SHIFT			4
-#define VIVS_DE_VR_CONFIG_EX_FILTER_TAP(x)			((x) << 4)
+#define VIVS_DE_VR_CONFIG_EX_FILTER_TAP(x)			(((x) << VIVS_DE_VR_CONFIG_EX_FILTER_TAP__SHIFT) & VIVS_DE_VR_CONFIG_EX_FILTER_TAP__MASK)
 #define VIVS_DE_VR_CONFIG_EX_FILTER_TAP_MASK			0x00000100
 
 #define VIVS_DE_PE_DITHER_LOW					0x000012e8
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__MASK			0x0000000f
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__SHIFT		0
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0(x)			((x) << 0)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__MASK			0x000000f0
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__SHIFT		4
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0(x)			((x) << 4)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__MASK			0x00000f00
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__SHIFT		8
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0(x)			((x) << 8)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__MASK			0x0000f000
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__SHIFT		12
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0(x)			((x) << 12)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__MASK			0x000f0000
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__SHIFT		16
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1(x)			((x) << 16)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__MASK			0x00f00000
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__SHIFT		20
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1(x)			((x) << 20)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__MASK			0x0f000000
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__SHIFT		24
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1(x)			((x) << 24)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__MASK)
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__MASK			0xf0000000
 #define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__SHIFT		28
-#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1(x)			((x) << 28)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__MASK)
 
 #define VIVS_DE_PE_DITHER_HIGH					0x000012ec
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__MASK		0x0000000f
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__SHIFT		0
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2(x)			((x) << 0)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__MASK		0x000000f0
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__SHIFT		4
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2(x)			((x) << 4)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__MASK		0x00000f00
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__SHIFT		8
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2(x)			((x) << 8)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__MASK		0x0000f000
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__SHIFT		12
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2(x)			((x) << 12)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__MASK		0x000f0000
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__SHIFT		16
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3(x)			((x) << 16)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__MASK		0x00f00000
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__SHIFT		20
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3(x)			((x) << 20)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__MASK		0x0f000000
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__SHIFT		24
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3(x)			((x) << 24)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__MASK)
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__MASK		0xf0000000
 #define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__SHIFT		28
-#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3(x)			((x) << 28)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__MASK)
 
 #define VIVS_DE_BW_CONFIG					0x000012f0
 #define VIVS_DE_BW_CONFIG_BLOCK_CONFIG__MASK			0x00000001
@@ -1389,26 +1389,26 @@ Copyright (C) 2013
 #define VIVS_DE_BW_BLOCK_SIZE					0x000012f4
 #define VIVS_DE_BW_BLOCK_SIZE_WIDTH__MASK			0x0000ffff
 #define VIVS_DE_BW_BLOCK_SIZE_WIDTH__SHIFT			0
-#define VIVS_DE_BW_BLOCK_SIZE_WIDTH(x)				((x) << 0)
+#define VIVS_DE_BW_BLOCK_SIZE_WIDTH(x)				(((x) << VIVS_DE_BW_BLOCK_SIZE_WIDTH__SHIFT) & VIVS_DE_BW_BLOCK_SIZE_WIDTH__MASK)
 #define VIVS_DE_BW_BLOCK_SIZE_HEIGHT__MASK			0xffff0000
 #define VIVS_DE_BW_BLOCK_SIZE_HEIGHT__SHIFT			16
-#define VIVS_DE_BW_BLOCK_SIZE_HEIGHT(x)				((x) << 16)
+#define VIVS_DE_BW_BLOCK_SIZE_HEIGHT(x)				(((x) << VIVS_DE_BW_BLOCK_SIZE_HEIGHT__SHIFT) & VIVS_DE_BW_BLOCK_SIZE_HEIGHT__MASK)
 
 #define VIVS_DE_BW_TILE_SIZE					0x000012f8
 #define VIVS_DE_BW_TILE_SIZE_WIDTH__MASK			0x0000ffff
 #define VIVS_DE_BW_TILE_SIZE_WIDTH__SHIFT			0
-#define VIVS_DE_BW_TILE_SIZE_WIDTH(x)				((x) << 0)
+#define VIVS_DE_BW_TILE_SIZE_WIDTH(x)				(((x) << VIVS_DE_BW_TILE_SIZE_WIDTH__SHIFT) & VIVS_DE_BW_TILE_SIZE_WIDTH__MASK)
 #define VIVS_DE_BW_TILE_SIZE_HEIGHT__MASK			0xffff0000
 #define VIVS_DE_BW_TILE_SIZE_HEIGHT__SHIFT			16
-#define VIVS_DE_BW_TILE_SIZE_HEIGHT(x)				((x) << 16)
+#define VIVS_DE_BW_TILE_SIZE_HEIGHT(x)				(((x) << VIVS_DE_BW_TILE_SIZE_HEIGHT__SHIFT) & VIVS_DE_BW_TILE_SIZE_HEIGHT__MASK)
 
 #define VIVS_DE_BW_BLOCK_MASK					0x000012fc
 #define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__MASK			0x0000ffff
 #define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__SHIFT			0
-#define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL(x)			((x) << 0)
+#define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL(x)			(((x) << VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__SHIFT) & VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__MASK)
 #define VIVS_DE_BW_BLOCK_MASK_VERTICAL__MASK			0xffff0000
 #define VIVS_DE_BW_BLOCK_MASK_VERTICAL__SHIFT			16
-#define VIVS_DE_BW_BLOCK_MASK_VERTICAL(x)			((x) << 16)
+#define VIVS_DE_BW_BLOCK_MASK_VERTICAL(x)			(((x) << VIVS_DE_BW_BLOCK_MASK_VERTICAL__SHIFT) & VIVS_DE_BW_BLOCK_MASK_VERTICAL__MASK)
 
 #define VIVS_DE_SRC_EX_CONFIG					0x00001300
 #define VIVS_DE_SRC_EX_CONFIG_MULTI_TILED__MASK			0x00000001
@@ -1429,7 +1429,7 @@ Copyright (C) 2013
 #define VIVS_DE_DE_MULTI_SOURCE					0x00001308
 #define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__MASK		0x00000007
 #define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__SHIFT		0
-#define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE(x)			((x) << 0)
+#define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE(x)			(((x) << VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__SHIFT) & VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__MASK)
 #define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK__MASK		0x00000700
 #define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK__SHIFT		8
 #define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL16	0x00000000
@@ -1458,63 +1458,63 @@ Copyright (C) 2013
 #define VIVS_DE_DEYUV_CONVERSION_ENABLE_PLANE3			0x00000003
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__MASK		0x0000000c
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__SHIFT		2
-#define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT(x)		((x) << 2)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__MASK		0x00000030
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__SHIFT		4
-#define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT(x)		((x) << 4)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__MASK		0x000000c0
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__SHIFT		6
-#define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT(x)		((x) << 6)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__MASK		0x00000300
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__SHIFT	8
-#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B(x)		((x) << 8)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__MASK		0x00000c00
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__SHIFT	10
-#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G(x)		((x) << 10)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__MASK		0x00003000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__SHIFT	12
-#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R(x)		((x) << 12)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__MASK		0x0000c000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__SHIFT	14
-#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A(x)		((x) << 14)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__MASK		0x00030000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__SHIFT	16
-#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B(x)		((x) << 16)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__MASK		0x000c0000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__SHIFT	18
-#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G(x)		((x) << 18)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__MASK		0x00300000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__SHIFT	20
-#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R(x)		((x) << 20)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__MASK		0x00c00000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__SHIFT	22
-#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A(x)		((x) << 22)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__MASK		0x03000000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__SHIFT	24
-#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B(x)		((x) << 24)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__MASK		0x0c000000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__SHIFT	26
-#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G(x)		((x) << 26)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__MASK		0x30000000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__SHIFT	28
-#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R(x)		((x) << 28)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__MASK)
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__MASK		0xc0000000
 #define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__SHIFT	30
-#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A(x)		((x) << 30)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__MASK)
 
 #define VIVS_DE_DE_PLANE2_ADDRESS				0x00001310
 
 #define VIVS_DE_DE_PLANE2_STRIDE				0x00001314
 #define VIVS_DE_DE_PLANE2_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_DE_PLANE2_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_DE_PLANE2_STRIDE_STRIDE(x)			((x) << 0)
+#define VIVS_DE_DE_PLANE2_STRIDE_STRIDE(x)			(((x) << VIVS_DE_DE_PLANE2_STRIDE_STRIDE__SHIFT) & VIVS_DE_DE_PLANE2_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_DE_PLANE3_ADDRESS				0x00001318
 
 #define VIVS_DE_DE_PLANE3_STRIDE				0x0000131c
 #define VIVS_DE_DE_PLANE3_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_DE_PLANE3_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_DE_PLANE3_STRIDE_STRIDE(x)			((x) << 0)
+#define VIVS_DE_DE_PLANE3_STRIDE_STRIDE(x)			(((x) << VIVS_DE_DE_PLANE3_STRIDE_STRIDE__SHIFT) & VIVS_DE_DE_PLANE3_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_DE_STALL_DE					0x00001320
 #define VIVS_DE_DE_STALL_DE_ENABLE__MASK			0x00000001
@@ -1527,10 +1527,10 @@ Copyright (C) 2013
 #define VIVS_DE_FILTER_KERNEL__LEN				0x00000080
 #define VIVS_DE_FILTER_KERNEL_COEFFICIENT0__MASK		0x0000ffff
 #define VIVS_DE_FILTER_KERNEL_COEFFICIENT0__SHIFT		0
-#define VIVS_DE_FILTER_KERNEL_COEFFICIENT0(x)			((x) << 0)
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT0(x)			(((x) << VIVS_DE_FILTER_KERNEL_COEFFICIENT0__SHIFT) & VIVS_DE_FILTER_KERNEL_COEFFICIENT0__MASK)
 #define VIVS_DE_FILTER_KERNEL_COEFFICIENT1__MASK		0xffff0000
 #define VIVS_DE_FILTER_KERNEL_COEFFICIENT1__SHIFT		16
-#define VIVS_DE_FILTER_KERNEL_COEFFICIENT1(x)			((x) << 16)
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT1(x)			(((x) << VIVS_DE_FILTER_KERNEL_COEFFICIENT1__SHIFT) & VIVS_DE_FILTER_KERNEL_COEFFICIENT1__MASK)
 
 #define VIVS_DE_INDEX_COLOR_TABLE(i0)			       (0x00001c00 + 0x4*(i0))
 #define VIVS_DE_INDEX_COLOR_TABLE__ESIZE			0x00000004
@@ -1541,20 +1541,20 @@ Copyright (C) 2013
 #define VIVS_DE_HORI_FILTER_KERNEL__LEN				0x00000080
 #define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__MASK		0x0000ffff
 #define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__SHIFT		0
-#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0(x)		((x) << 0)
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0(x)		(((x) << VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__SHIFT) & VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__MASK)
 #define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__MASK		0xffff0000
 #define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__SHIFT		16
-#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1(x)		((x) << 16)
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1(x)		(((x) << VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__SHIFT) & VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__MASK)
 
 #define VIVS_DE_VERTI_FILTER_KERNEL(i0)			       (0x00002a00 + 0x4*(i0))
 #define VIVS_DE_VERTI_FILTER_KERNEL__ESIZE			0x00000004
 #define VIVS_DE_VERTI_FILTER_KERNEL__LEN			0x00000080
 #define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__MASK		0x0000ffff
 #define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__SHIFT		0
-#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0(x)		((x) << 0)
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0(x)		(((x) << VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__SHIFT) & VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__MASK)
 #define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__MASK		0xffff0000
 #define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__SHIFT		16
-#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1(x)		((x) << 16)
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1(x)		(((x) << VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__SHIFT) & VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__MASK)
 
 #define VIVS_DE_INDEX_COLOR_TABLE32(i0)			       (0x00003400 + 0x4*(i0))
 #define VIVS_DE_INDEX_COLOR_TABLE32__ESIZE			0x00000004
@@ -1571,14 +1571,14 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK4_SRC_STRIDE__LEN				0x00000004
 #define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE(x)			((x) << 0)
+#define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE(x)			(((x) << VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__SHIFT) & VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG(i0)		       (0x00012820 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG__ESIZE		0x00000004
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG__LEN			0x00000004
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__MASK		0x0000ffff
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__SHIFT		0
-#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH(x)		((x) << 0)
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH(x)		(((x) << VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__MASK)
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION__MASK	0x00010000
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION__SHIFT	16
 #define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_DISABLE	0x00000000
@@ -1611,37 +1611,37 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND	0x00008000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__MASK			0x00300000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__SHIFT		20
-#define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE(x)			((x) << 20)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE(x)			(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__MASK)
 #define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__MASK		0x1f000000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__SHIFT		24
-#define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT(x)		((x) << 24)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT(x)		(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__MASK)
 #define VIVS_DE_BLOCK4_SRC_CONFIG_DISABLE420_L2_CACHE__MASK	0x20000000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_DISABLE420_L2_CACHE__SHIFT	29
 #define VIVS_DE_BLOCK4_SRC_CONFIG_DISABLE420_L2_CACHE_DISABLE	0x00000000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_DISABLE420_L2_CACHE_ENABLE	0x20000000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__MASK		0xc0000000
 #define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__SHIFT		30
-#define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL(x)		((x) << 30)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL(x)		(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__MASK)
 
 #define VIVS_DE_BLOCK4_SRC_ORIGIN(i0)			       (0x00012840 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_SRC_ORIGIN__ESIZE			0x00000004
 #define VIVS_DE_BLOCK4_SRC_ORIGIN__LEN				0x00000004
 #define VIVS_DE_BLOCK4_SRC_ORIGIN_X__MASK			0x0000ffff
 #define VIVS_DE_BLOCK4_SRC_ORIGIN_X__SHIFT			0
-#define VIVS_DE_BLOCK4_SRC_ORIGIN_X(x)				((x) << 0)
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_X(x)				(((x) << VIVS_DE_BLOCK4_SRC_ORIGIN_X__SHIFT) & VIVS_DE_BLOCK4_SRC_ORIGIN_X__MASK)
 #define VIVS_DE_BLOCK4_SRC_ORIGIN_Y__MASK			0xffff0000
 #define VIVS_DE_BLOCK4_SRC_ORIGIN_Y__SHIFT			16
-#define VIVS_DE_BLOCK4_SRC_ORIGIN_Y(x)				((x) << 16)
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_Y(x)				(((x) << VIVS_DE_BLOCK4_SRC_ORIGIN_Y__SHIFT) & VIVS_DE_BLOCK4_SRC_ORIGIN_Y__MASK)
 
 #define VIVS_DE_BLOCK4_SRC_SIZE(i0)			       (0x00012850 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_SRC_SIZE__ESIZE				0x00000004
 #define VIVS_DE_BLOCK4_SRC_SIZE__LEN				0x00000004
 #define VIVS_DE_BLOCK4_SRC_SIZE_X__MASK				0x0000ffff
 #define VIVS_DE_BLOCK4_SRC_SIZE_X__SHIFT			0
-#define VIVS_DE_BLOCK4_SRC_SIZE_X(x)				((x) << 0)
+#define VIVS_DE_BLOCK4_SRC_SIZE_X(x)				(((x) << VIVS_DE_BLOCK4_SRC_SIZE_X__SHIFT) & VIVS_DE_BLOCK4_SRC_SIZE_X__MASK)
 #define VIVS_DE_BLOCK4_SRC_SIZE_Y__MASK				0xffff0000
 #define VIVS_DE_BLOCK4_SRC_SIZE_Y__SHIFT			16
-#define VIVS_DE_BLOCK4_SRC_SIZE_Y(x)				((x) << 16)
+#define VIVS_DE_BLOCK4_SRC_SIZE_Y(x)				(((x) << VIVS_DE_BLOCK4_SRC_SIZE_Y__SHIFT) & VIVS_DE_BLOCK4_SRC_SIZE_Y__MASK)
 
 #define VIVS_DE_BLOCK4_SRC_COLOR_BG(i0)			       (0x00012860 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_SRC_COLOR_BG__ESIZE			0x00000004
@@ -1652,10 +1652,10 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK4_ROP__LEN					0x00000004
 #define VIVS_DE_BLOCK4_ROP_ROP_FG__MASK				0x000000ff
 #define VIVS_DE_BLOCK4_ROP_ROP_FG__SHIFT			0
-#define VIVS_DE_BLOCK4_ROP_ROP_FG(x)				((x) << 0)
+#define VIVS_DE_BLOCK4_ROP_ROP_FG(x)				(((x) << VIVS_DE_BLOCK4_ROP_ROP_FG__SHIFT) & VIVS_DE_BLOCK4_ROP_ROP_FG__MASK)
 #define VIVS_DE_BLOCK4_ROP_ROP_BG__MASK				0x0000ff00
 #define VIVS_DE_BLOCK4_ROP_ROP_BG__SHIFT			8
-#define VIVS_DE_BLOCK4_ROP_ROP_BG(x)				((x) << 8)
+#define VIVS_DE_BLOCK4_ROP_ROP_BG(x)				(((x) << VIVS_DE_BLOCK4_ROP_ROP_BG__SHIFT) & VIVS_DE_BLOCK4_ROP_ROP_BG__MASK)
 #define VIVS_DE_BLOCK4_ROP_TYPE__MASK				0x00300000
 #define VIVS_DE_BLOCK4_ROP_TYPE__SHIFT				20
 #define VIVS_DE_BLOCK4_ROP_TYPE_ROP2_PATTERN			0x00000000
@@ -1694,14 +1694,14 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED	0x00002000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__MASK	0x07000000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT	24
-#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE(x)		((x) << 24)
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__MASK)
 #define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR__MASK	0x08000000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR__SHIFT	27
 #define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLE	0x00000000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLE	0x08000000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__MASK	0x70000000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__SHIFT	28
-#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE(x)		((x) << 28)
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__MASK)
 #define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR__MASK	0x80000000
 #define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR__SHIFT	31
 #define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLE	0x00000000
@@ -1716,7 +1716,7 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK4_STRIDE_U__LEN				0x00000004
 #define VIVS_DE_BLOCK4_STRIDE_U_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_BLOCK4_STRIDE_U_STRIDE__SHIFT			0
-#define VIVS_DE_BLOCK4_STRIDE_U_STRIDE(x)			((x) << 0)
+#define VIVS_DE_BLOCK4_STRIDE_U_STRIDE(x)			(((x) << VIVS_DE_BLOCK4_STRIDE_U_STRIDE__SHIFT) & VIVS_DE_BLOCK4_STRIDE_U_STRIDE__MASK)
 
 #define VIVS_DE_BLOCK4_ADDRESS_V(i0)			       (0x000128c0 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_ADDRESS_V__ESIZE				0x00000004
@@ -1727,33 +1727,33 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK4_STRIDE_V__LEN				0x00000004
 #define VIVS_DE_BLOCK4_STRIDE_V_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_BLOCK4_STRIDE_V_STRIDE__SHIFT			0
-#define VIVS_DE_BLOCK4_STRIDE_V_STRIDE(x)			((x) << 0)
+#define VIVS_DE_BLOCK4_STRIDE_V_STRIDE(x)			(((x) << VIVS_DE_BLOCK4_STRIDE_V_STRIDE__SHIFT) & VIVS_DE_BLOCK4_STRIDE_V_STRIDE__MASK)
 
 #define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT(i0)		       (0x000128e0 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT__ESIZE		0x00000004
 #define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT__LEN			0x00000004
 #define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
 #define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT	0
-#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT(x)		((x) << 0)
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT(x)		(((x) << VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__MASK)
 
 #define VIVS_DE_BLOCK4_ROT_ANGLE(i0)			       (0x000128f0 + 0x4*(i0))
 #define VIVS_DE_BLOCK4_ROT_ANGLE__ESIZE				0x00000004
 #define VIVS_DE_BLOCK4_ROT_ANGLE__LEN				0x00000004
 #define VIVS_DE_BLOCK4_ROT_ANGLE_SRC__MASK			0x00000007
 #define VIVS_DE_BLOCK4_ROT_ANGLE_SRC__SHIFT			0
-#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC(x)				((x) << 0)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC(x)				(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_SRC__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_SRC__MASK)
 #define VIVS_DE_BLOCK4_ROT_ANGLE_DST__MASK			0x00000038
 #define VIVS_DE_BLOCK4_ROT_ANGLE_DST__SHIFT			3
-#define VIVS_DE_BLOCK4_ROT_ANGLE_DST(x)				((x) << 3)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST(x)				(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_DST__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_DST__MASK)
 #define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MASK			0x00000100
 #define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MASK			0x00000200
 #define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__MASK		0x00003000
 #define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__SHIFT		12
-#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR(x)			((x) << 12)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR(x)			(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__MASK)
 #define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR_MASK		0x00008000
 #define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__MASK		0x00030000
 #define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__SHIFT		16
-#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR(x)			((x) << 16)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR(x)			(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__MASK)
 #define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR_MASK		0x00080000
 
 #define VIVS_DE_BLOCK4_GLOBAL_SRC_COLOR(i0)		       (0x00012900 + 0x4*(i0))
@@ -1880,14 +1880,14 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK8_SRC_STRIDE__LEN				0x00000008
 #define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__SHIFT			0
-#define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE(x)			((x) << 0)
+#define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE(x)			(((x) << VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__SHIFT) & VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__MASK)
 
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG(i0)		       (0x00012a40 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG__ESIZE		0x00000004
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG__LEN			0x00000008
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__MASK		0x0000ffff
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__SHIFT		0
-#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH(x)		((x) << 0)
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH(x)		(((x) << VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__MASK)
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION__MASK	0x00010000
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION__SHIFT	16
 #define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_DISABLE	0x00000000
@@ -1920,37 +1920,37 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND	0x00008000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__MASK			0x00300000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__SHIFT		20
-#define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE(x)			((x) << 20)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE(x)			(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__MASK)
 #define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__MASK		0x1f000000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__SHIFT		24
-#define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT(x)		((x) << 24)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT(x)		(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__MASK)
 #define VIVS_DE_BLOCK8_SRC_CONFIG_DISABLE420_L2_CACHE__MASK	0x20000000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_DISABLE420_L2_CACHE__SHIFT	29
 #define VIVS_DE_BLOCK8_SRC_CONFIG_DISABLE420_L2_CACHE_DISABLE	0x00000000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_DISABLE420_L2_CACHE_ENABLE	0x20000000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__MASK		0xc0000000
 #define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__SHIFT		30
-#define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL(x)		((x) << 30)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL(x)		(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__MASK)
 
 #define VIVS_DE_BLOCK8_SRC_ORIGIN(i0)			       (0x00012a80 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_SRC_ORIGIN__ESIZE			0x00000004
 #define VIVS_DE_BLOCK8_SRC_ORIGIN__LEN				0x00000008
 #define VIVS_DE_BLOCK8_SRC_ORIGIN_X__MASK			0x0000ffff
 #define VIVS_DE_BLOCK8_SRC_ORIGIN_X__SHIFT			0
-#define VIVS_DE_BLOCK8_SRC_ORIGIN_X(x)				((x) << 0)
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_X(x)				(((x) << VIVS_DE_BLOCK8_SRC_ORIGIN_X__SHIFT) & VIVS_DE_BLOCK8_SRC_ORIGIN_X__MASK)
 #define VIVS_DE_BLOCK8_SRC_ORIGIN_Y__MASK			0xffff0000
 #define VIVS_DE_BLOCK8_SRC_ORIGIN_Y__SHIFT			16
-#define VIVS_DE_BLOCK8_SRC_ORIGIN_Y(x)				((x) << 16)
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_Y(x)				(((x) << VIVS_DE_BLOCK8_SRC_ORIGIN_Y__SHIFT) & VIVS_DE_BLOCK8_SRC_ORIGIN_Y__MASK)
 
 #define VIVS_DE_BLOCK8_SRC_SIZE(i0)			       (0x00012aa0 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_SRC_SIZE__ESIZE				0x00000004
 #define VIVS_DE_BLOCK8_SRC_SIZE__LEN				0x00000008
 #define VIVS_DE_BLOCK8_SRC_SIZE_X__MASK				0x0000ffff
 #define VIVS_DE_BLOCK8_SRC_SIZE_X__SHIFT			0
-#define VIVS_DE_BLOCK8_SRC_SIZE_X(x)				((x) << 0)
+#define VIVS_DE_BLOCK8_SRC_SIZE_X(x)				(((x) << VIVS_DE_BLOCK8_SRC_SIZE_X__SHIFT) & VIVS_DE_BLOCK8_SRC_SIZE_X__MASK)
 #define VIVS_DE_BLOCK8_SRC_SIZE_Y__MASK				0xffff0000
 #define VIVS_DE_BLOCK8_SRC_SIZE_Y__SHIFT			16
-#define VIVS_DE_BLOCK8_SRC_SIZE_Y(x)				((x) << 16)
+#define VIVS_DE_BLOCK8_SRC_SIZE_Y(x)				(((x) << VIVS_DE_BLOCK8_SRC_SIZE_Y__SHIFT) & VIVS_DE_BLOCK8_SRC_SIZE_Y__MASK)
 
 #define VIVS_DE_BLOCK8_SRC_COLOR_BG(i0)			       (0x00012ac0 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_SRC_COLOR_BG__ESIZE			0x00000004
@@ -1961,10 +1961,10 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK8_ROP__LEN					0x00000008
 #define VIVS_DE_BLOCK8_ROP_ROP_FG__MASK				0x000000ff
 #define VIVS_DE_BLOCK8_ROP_ROP_FG__SHIFT			0
-#define VIVS_DE_BLOCK8_ROP_ROP_FG(x)				((x) << 0)
+#define VIVS_DE_BLOCK8_ROP_ROP_FG(x)				(((x) << VIVS_DE_BLOCK8_ROP_ROP_FG__SHIFT) & VIVS_DE_BLOCK8_ROP_ROP_FG__MASK)
 #define VIVS_DE_BLOCK8_ROP_ROP_BG__MASK				0x0000ff00
 #define VIVS_DE_BLOCK8_ROP_ROP_BG__SHIFT			8
-#define VIVS_DE_BLOCK8_ROP_ROP_BG(x)				((x) << 8)
+#define VIVS_DE_BLOCK8_ROP_ROP_BG(x)				(((x) << VIVS_DE_BLOCK8_ROP_ROP_BG__SHIFT) & VIVS_DE_BLOCK8_ROP_ROP_BG__MASK)
 #define VIVS_DE_BLOCK8_ROP_TYPE__MASK				0x00300000
 #define VIVS_DE_BLOCK8_ROP_TYPE__SHIFT				20
 #define VIVS_DE_BLOCK8_ROP_TYPE_ROP2_PATTERN			0x00000000
@@ -2003,14 +2003,14 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED	0x00002000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__MASK	0x07000000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT	24
-#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE(x)		((x) << 24)
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__MASK)
 #define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR__MASK	0x08000000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR__SHIFT	27
 #define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLE	0x00000000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLE	0x08000000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__MASK	0x70000000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__SHIFT	28
-#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE(x)		((x) << 28)
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__MASK)
 #define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR__MASK	0x80000000
 #define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR__SHIFT	31
 #define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLE	0x00000000
@@ -2025,7 +2025,7 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK8_STRIDE_U__LEN				0x00000008
 #define VIVS_DE_BLOCK8_STRIDE_U_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_BLOCK8_STRIDE_U_STRIDE__SHIFT			0
-#define VIVS_DE_BLOCK8_STRIDE_U_STRIDE(x)			((x) << 0)
+#define VIVS_DE_BLOCK8_STRIDE_U_STRIDE(x)			(((x) << VIVS_DE_BLOCK8_STRIDE_U_STRIDE__SHIFT) & VIVS_DE_BLOCK8_STRIDE_U_STRIDE__MASK)
 
 #define VIVS_DE_BLOCK8_ADDRESS_V(i0)			       (0x00012b80 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_ADDRESS_V__ESIZE				0x00000004
@@ -2036,33 +2036,33 @@ Copyright (C) 2013
 #define VIVS_DE_BLOCK8_STRIDE_V__LEN				0x00000008
 #define VIVS_DE_BLOCK8_STRIDE_V_STRIDE__MASK			0x0003ffff
 #define VIVS_DE_BLOCK8_STRIDE_V_STRIDE__SHIFT			0
-#define VIVS_DE_BLOCK8_STRIDE_V_STRIDE(x)			((x) << 0)
+#define VIVS_DE_BLOCK8_STRIDE_V_STRIDE(x)			(((x) << VIVS_DE_BLOCK8_STRIDE_V_STRIDE__SHIFT) & VIVS_DE_BLOCK8_STRIDE_V_STRIDE__MASK)
 
 #define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT(i0)		       (0x00012bc0 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT__ESIZE		0x00000004
 #define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT__LEN			0x00000008
 #define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
 #define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT	0
-#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT(x)		((x) << 0)
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT(x)		(((x) << VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__MASK)
 
 #define VIVS_DE_BLOCK8_ROT_ANGLE(i0)			       (0x00012be0 + 0x4*(i0))
 #define VIVS_DE_BLOCK8_ROT_ANGLE__ESIZE				0x00000004
 #define VIVS_DE_BLOCK8_ROT_ANGLE__LEN				0x00000008
 #define VIVS_DE_BLOCK8_ROT_ANGLE_SRC__MASK			0x00000007
 #define VIVS_DE_BLOCK8_ROT_ANGLE_SRC__SHIFT			0
-#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC(x)				((x) << 0)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC(x)				(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_SRC__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_SRC__MASK)
 #define VIVS_DE_BLOCK8_ROT_ANGLE_DST__MASK			0x00000038
 #define VIVS_DE_BLOCK8_ROT_ANGLE_DST__SHIFT			3
-#define VIVS_DE_BLOCK8_ROT_ANGLE_DST(x)				((x) << 3)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST(x)				(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_DST__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_DST__MASK)
 #define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MASK			0x00000100
 #define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MASK			0x00000200
 #define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__MASK		0x00003000
 #define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__SHIFT		12
-#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR(x)			((x) << 12)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR(x)			(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__MASK)
 #define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR_MASK		0x00008000
 #define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__MASK		0x00030000
 #define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__SHIFT		16
-#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR(x)			((x) << 16)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR(x)			(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__MASK)
 #define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR_MASK		0x00080000
 
 #define VIVS_DE_BLOCK8_GLOBAL_SRC_COLOR(i0)		       (0x00012c00 + 0x4*(i0))
@@ -2187,29 +2187,47 @@ Copyright (C) 2013
 #define VIVS_VS_INPUT_COUNT					0x00000808
 #define VIVS_VS_INPUT_COUNT_COUNT__MASK				0x0000000f
 #define VIVS_VS_INPUT_COUNT_COUNT__SHIFT			0
-#define VIVS_VS_INPUT_COUNT_COUNT(x)				((x) << 0)
+#define VIVS_VS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK)
 #define VIVS_VS_INPUT_COUNT_UNK8__MASK				0x00001f00
 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT				8
-#define VIVS_VS_INPUT_COUNT_UNK8(x)				((x) << 8)
+#define VIVS_VS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK)
 
 #define VIVS_VS_TEMP_REGISTER_CONTROL				0x0000080c
 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
-#define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		((x) << 0)
+#define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
 
 #define VIVS_VS_OUTPUT(i0)				       (0x00000810 + 0x4*(i0))
 #define VIVS_VS_OUTPUT__ESIZE					0x00000004
 #define VIVS_VS_OUTPUT__LEN					0x00000004
-#define VIVS_VS_OUTPUT_UNK0__MASK				0x0000ffff
-#define VIVS_VS_OUTPUT_UNK0__SHIFT				0
-#define VIVS_VS_OUTPUT_UNK0(x)					((x) << 0)
-#define VIVS_VS_OUTPUT_UNK16__MASK				0xffff0000
-#define VIVS_VS_OUTPUT_UNK16__SHIFT				16
-#define VIVS_VS_OUTPUT_UNK16(x)					((x) << 16)
+#define VIVS_VS_OUTPUT_O0__MASK					0x000000ff
+#define VIVS_VS_OUTPUT_O0__SHIFT				0
+#define VIVS_VS_OUTPUT_O0(x)					(((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK)
+#define VIVS_VS_OUTPUT_O1__MASK					0x0000ff00
+#define VIVS_VS_OUTPUT_O1__SHIFT				8
+#define VIVS_VS_OUTPUT_O1(x)					(((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK)
+#define VIVS_VS_OUTPUT_O2__MASK					0x00ff0000
+#define VIVS_VS_OUTPUT_O2__SHIFT				16
+#define VIVS_VS_OUTPUT_O2(x)					(((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK)
+#define VIVS_VS_OUTPUT_O3__MASK					0xff000000
+#define VIVS_VS_OUTPUT_O3__SHIFT				24
+#define VIVS_VS_OUTPUT_O3(x)					(((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK)
 
 #define VIVS_VS_INPUT(i0)				       (0x00000820 + 0x4*(i0))
 #define VIVS_VS_INPUT__ESIZE					0x00000004
 #define VIVS_VS_INPUT__LEN					0x00000004
+#define VIVS_VS_INPUT_I0__MASK					0x000000ff
+#define VIVS_VS_INPUT_I0__SHIFT					0
+#define VIVS_VS_INPUT_I0(x)					(((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK)
+#define VIVS_VS_INPUT_I1__MASK					0x0000ff00
+#define VIVS_VS_INPUT_I1__SHIFT					8
+#define VIVS_VS_INPUT_I1(x)					(((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK)
+#define VIVS_VS_INPUT_I2__MASK					0x00ff0000
+#define VIVS_VS_INPUT_I2__SHIFT					16
+#define VIVS_VS_INPUT_I2(x)					(((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK)
+#define VIVS_VS_INPUT_I3__MASK					0xff000000
+#define VIVS_VS_INPUT_I3__SHIFT					24
+#define VIVS_VS_INPUT_I3(x)					(((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK)
 
 #define VIVS_VS_LOAD_BALANCING					0x00000830
 
@@ -2278,10 +2296,10 @@ Copyright (C) 2013
 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT				0x00000a30
 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK		0x000000ff
 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT		0
-#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x)			((x) << 0)
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x)			(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK)
 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK		0x0000ff00
 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT		8
-#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x)		((x) << 8)
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x)		(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK)
 
 #define VIVS_PA_CONFIG						0x00000a34
 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE			0x00000004
@@ -2317,10 +2335,10 @@ Copyright (C) 2013
 #define VIVS_PA_SHADER_ATTRIBUTES__LEN				0x0000000a
 #define VIVS_PA_SHADER_ATTRIBUTES_UNK0__MASK			0x000000ff
 #define VIVS_PA_SHADER_ATTRIBUTES_UNK0__SHIFT			0
-#define VIVS_PA_SHADER_ATTRIBUTES_UNK0(x)			((x) << 0)
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK0(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK0__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK0__MASK)
 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK			0x0000ff00
 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT			8
-#define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x)			((x) << 8)
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK)
 
 #define VIVS_PA_VIEWPORT_UNK00A80				0x00000a80
 
@@ -2375,15 +2393,15 @@ Copyright (C) 2013
 #define VIVS_PS_INPUT_COUNT					0x00001008
 #define VIVS_PS_INPUT_COUNT_COUNT__MASK				0x0000000f
 #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT			0
-#define VIVS_PS_INPUT_COUNT_COUNT(x)				((x) << 0)
+#define VIVS_PS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK)
 #define VIVS_PS_INPUT_COUNT_UNK8__MASK				0x00001f00
 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT				8
-#define VIVS_PS_INPUT_COUNT_UNK8(x)				((x) << 8)
+#define VIVS_PS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK)
 
 #define VIVS_PS_TEMP_REGISTER_CONTROL				0x0000100c
 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
-#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		((x) << 0)
+#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
 
 #define VIVS_PS_CONTROL						0x00001010
 #define VIVS_PS_CONTROL_BYPASS					0x00000001
@@ -2417,7 +2435,7 @@ Copyright (C) 2013
 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK			0x00000020
 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK			0x00000700
 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT			8
-#define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x)			((x) << 8)
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x)			(((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK)
 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK			0x00000800
 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE			0x00001000
 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK			0x00002000
@@ -2441,35 +2459,35 @@ Copyright (C) 2013
 #define VIVS_PE_STENCIL_OP					0x00001418
 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK			0x00000007
 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT			0
-#define VIVS_PE_STENCIL_OP_FUNC_FRONT(x)			((x) << 0)
+#define VIVS_PE_STENCIL_OP_FUNC_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK)
 #define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK			0x00000008
 #define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK			0x00000070
 #define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT			4
-#define VIVS_PE_STENCIL_OP_PASS_FRONT(x)			((x) << 4)
+#define VIVS_PE_STENCIL_OP_PASS_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK)
 #define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK			0x00000080
 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK			0x00000700
 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT			8
-#define VIVS_PE_STENCIL_OP_FAIL_FRONT(x)			((x) << 8)
+#define VIVS_PE_STENCIL_OP_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK)
 #define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK			0x00000800
 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK		0x00007000
 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT		12
-#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x)			((x) << 12)
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK)
 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK		0x00008000
 #define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK			0x00070000
 #define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT			16
-#define VIVS_PE_STENCIL_OP_FUNC_BACK(x)				((x) << 16)
+#define VIVS_PE_STENCIL_OP_FUNC_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK)
 #define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK			0x00080000
 #define VIVS_PE_STENCIL_OP_PASS_BACK__MASK			0x00700000
 #define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT			20
-#define VIVS_PE_STENCIL_OP_PASS_BACK(x)				((x) << 20)
+#define VIVS_PE_STENCIL_OP_PASS_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK)
 #define VIVS_PE_STENCIL_OP_PASS_BACK_MASK			0x00800000
 #define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK			0x07000000
 #define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT			24
-#define VIVS_PE_STENCIL_OP_FAIL_BACK(x)				((x) << 24)
+#define VIVS_PE_STENCIL_OP_FAIL_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK)
 #define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK			0x08000000
 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK		0x70000000
 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT		28
-#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x)			((x) << 28)
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK)
 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK			0x80000000
 
 #define VIVS_PE_STENCIL_CONFIG					0x0000141c
@@ -2484,35 +2502,35 @@ Copyright (C) 2013
 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK			0x00000080
 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK			0x0000ff00
 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT			8
-#define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x)			((x) << 8)
+#define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK)
 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK			0x00ff0000
 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT		16
-#define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x)			((x) << 16)
+#define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK)
 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK__MASK			0xff000000
 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK__SHIFT		24
-#define VIVS_PE_STENCIL_CONFIG_WRITE_MASK(x)			((x) << 24)
+#define VIVS_PE_STENCIL_CONFIG_WRITE_MASK(x)			(((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK__MASK)
 
 #define VIVS_PE_ALPHA_OP					0x00001420
 #define VIVS_PE_ALPHA_OP_ALPHA_TEST				0x00000001
 #define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK			0x00000002
 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK			0x00000070
 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT			4
-#define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x)				((x) << 4)
+#define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK)
 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK			0x00000080
 
 #define VIVS_PE_ALPHA_BLEND_COLOR				0x00001424
 #define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK			0x000000ff
 #define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT			0
-#define VIVS_PE_ALPHA_BLEND_COLOR_B(x)				((x) << 0)
+#define VIVS_PE_ALPHA_BLEND_COLOR_B(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK)
 #define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK			0x0000ff00
 #define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT			8
-#define VIVS_PE_ALPHA_BLEND_COLOR_G(x)				((x) << 8)
+#define VIVS_PE_ALPHA_BLEND_COLOR_G(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK)
 #define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK			0x00ff0000
 #define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT			16
-#define VIVS_PE_ALPHA_BLEND_COLOR_R(x)				((x) << 16)
+#define VIVS_PE_ALPHA_BLEND_COLOR_R(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK)
 #define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK			0xff000000
 #define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT			24
-#define VIVS_PE_ALPHA_BLEND_COLOR_A(x)				((x) << 24)
+#define VIVS_PE_ALPHA_BLEND_COLOR_A(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK)
 
 #define VIVS_PE_ALPHA_CONFIG					0x00001428
 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR			0x00000001
@@ -2521,13 +2539,13 @@ Copyright (C) 2013
 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK		0x00000008
 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK		0x000000f0
 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT		4
-#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x)			((x) << 4)
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK)
 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK		0x00000f00
 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT		8
-#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x)			((x) << 8)
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK)
 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK			0x00007000
 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT			12
-#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x)			((x) << 12)
+#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK)
 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK			0x00008000
 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA			0x00010000
 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_ALPHA_MASK		0x00020000
@@ -2535,23 +2553,23 @@ Copyright (C) 2013
 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK		0x00080000
 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK		0x00f00000
 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT		20
-#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x)			((x) << 20)
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK)
 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK		0x0f000000
 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT		24
-#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x)			((x) << 24)
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK)
 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK			0x70000000
 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT			28
-#define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x)			((x) << 28)
+#define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK)
 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK			0x80000000
 
 #define VIVS_PE_COLOR_FORMAT					0x0000142c
 #define VIVS_PE_COLOR_FORMAT_FORMAT__MASK			0x0000000f
 #define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT			0
-#define VIVS_PE_COLOR_FORMAT_FORMAT(x)				((x) << 0)
+#define VIVS_PE_COLOR_FORMAT_FORMAT(x)				(((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK)
 #define VIVS_PE_COLOR_FORMAT_FORMAT_MASK			0x00000010
 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK			0x00000f00
 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT			8
-#define VIVS_PE_COLOR_FORMAT_COMPONENTS(x)			((x) << 8)
+#define VIVS_PE_COLOR_FORMAT_COMPONENTS(x)			(((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK)
 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK			0x00001000
 #define VIVS_PE_COLOR_FORMAT_PARTIAL				0x00010000
 #define VIVS_PE_COLOR_FORMAT_PARTIAL_MASK			0x00020000
@@ -2588,12 +2606,12 @@ Copyright (C) 2013
 #define VIVS_PE_STENCIL_CONFIG_EXT				0x000014a0
 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK		0x000000ff
 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT		0
-#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x)			((x) << 0)
+#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK)
 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK		0x00000100
 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK			0x00000200
 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK			0xffff0000
 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT			16
-#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x)			((x) << 16)
+#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK)
 
 #define VIVS_PE_LOGIC_OP					0x000014a4
 #define VIVS_PE_LOGIC_OP_OP__MASK				0x0000000f
@@ -2697,7 +2715,7 @@ Copyright (C) 2013
 #define VIVS_RS_CONFIG						0x00001604
 #define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK			0x0000001f
 #define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT			0
-#define VIVS_RS_CONFIG_SOURCE_FORMAT(x)				((x) << 0)
+#define VIVS_RS_CONFIG_SOURCE_FORMAT(x)				(((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK)
 #define VIVS_RS_CONFIG_DOWNSAMPLE__MASK				0x00000060
 #define VIVS_RS_CONFIG_DOWNSAMPLE__SHIFT			5
 #define VIVS_RS_CONFIG_DOWNSAMPLE_NONE				0x00000000
@@ -2707,7 +2725,7 @@ Copyright (C) 2013
 #define VIVS_RS_CONFIG_SOURCE_TILED				0x00000080
 #define VIVS_RS_CONFIG_DEST_FORMAT__MASK			0x00001f00
 #define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT			8
-#define VIVS_RS_CONFIG_DEST_FORMAT(x)				((x) << 8)
+#define VIVS_RS_CONFIG_DEST_FORMAT(x)				(((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK)
 #define VIVS_RS_CONFIG_DEST_TILED				0x00004000
 #define VIVS_RS_CONFIG_SWAP_RB					0x20000000
 #define VIVS_RS_CONFIG_FLIP					0x40000000
@@ -2717,7 +2735,7 @@ Copyright (C) 2013
 #define VIVS_RS_SOURCE_STRIDE					0x0000160c
 #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT			0
-#define VIVS_RS_SOURCE_STRIDE_STRIDE(x)				((x) << 0)
+#define VIVS_RS_SOURCE_STRIDE_STRIDE(x)				(((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK)
 #define VIVS_RS_SOURCE_STRIDE_TILING				0x80000000
 
 #define VIVS_RS_DEST_ADDR					0x00001610
@@ -2725,16 +2743,16 @@ Copyright (C) 2013
 #define VIVS_RS_DEST_STRIDE					0x00001614
 #define VIVS_RS_DEST_STRIDE_STRIDE__MASK			0x0003ffff
 #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT			0
-#define VIVS_RS_DEST_STRIDE_STRIDE(x)				((x) << 0)
+#define VIVS_RS_DEST_STRIDE_STRIDE(x)				(((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK)
 #define VIVS_RS_DEST_STRIDE_TILING				0x80000000
 
 #define VIVS_RS_WINDOW_SIZE					0x00001620
 #define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK			0xffff0000
 #define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT			16
-#define VIVS_RS_WINDOW_SIZE_HEIGHT(x)				((x) << 16)
+#define VIVS_RS_WINDOW_SIZE_HEIGHT(x)				(((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK)
 #define VIVS_RS_WINDOW_SIZE_WIDTH__MASK				0x0000ffff
 #define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT			0
-#define VIVS_RS_WINDOW_SIZE_WIDTH(x)				((x) << 0)
+#define VIVS_RS_WINDOW_SIZE_WIDTH(x)				(((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK)
 
 #define VIVS_RS_DITHER(i0)				       (0x00001630 + 0x4*(i0))
 #define VIVS_RS_DITHER__ESIZE					0x00000004
@@ -2743,7 +2761,7 @@ Copyright (C) 2013
 #define VIVS_RS_CLEAR_CONTROL					0x0000163c
 #define VIVS_RS_CLEAR_CONTROL_BITS__MASK			0x0000ffff
 #define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT			0
-#define VIVS_RS_CLEAR_CONTROL_BITS(x)				((x) << 0)
+#define VIVS_RS_CLEAR_CONTROL_BITS(x)				(((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK)
 #define VIVS_RS_CLEAR_CONTROL_MODE__MASK			0x00030000
 #define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT			16
 #define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED			0x00000000
@@ -2761,10 +2779,10 @@ Copyright (C) 2013
 #define VIVS_RS_EXTRA_CONFIG					0x000016a0
 #define VIVS_RS_EXTRA_CONFIG_AA__MASK				0x00000003
 #define VIVS_RS_EXTRA_CONFIG_AA__SHIFT				0
-#define VIVS_RS_EXTRA_CONFIG_AA(x)				((x) << 0)
+#define VIVS_RS_EXTRA_CONFIG_AA(x)				(((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK)
 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK			0x00000300
 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT			8
-#define VIVS_RS_EXTRA_CONFIG_ENDIAN(x)				((x) << 8)
+#define VIVS_RS_EXTRA_CONFIG_ENDIAN(x)				(((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK)
 
 #define VIVS_RS_UNK016B4					0x000016b4
 
@@ -2823,10 +2841,10 @@ Copyright (C) 2013
 #define VIVS_TS_SAMPLER_CONFIG(i0)			       (0x00001720 + 0x4*(i0))
 #define VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK			0x00000003
 #define VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT			0
-#define VIVS_TS_SAMPLER_CONFIG_ENABLE(x)			((x) << 0)
+#define VIVS_TS_SAMPLER_CONFIG_ENABLE(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT) & VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK)
 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK			0x000000f0
 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT			4
-#define VIVS_TS_SAMPLER_CONFIG_FORMAT(x)			((x) << 4)
+#define VIVS_TS_SAMPLER_CONFIG_FORMAT(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK)
 
 #define VIVS_TS_SAMPLER_STATUS_BASE(i0)			       (0x00001740 + 0x4*(i0))
 
@@ -2863,52 +2881,53 @@ Copyright (C) 2013
 #define VIVS_TE_SAMPLER_CONFIG0(i0)			       (0x00002000 + 0x4*(i0))
 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT			0
-#define VIVS_TE_SAMPLER_CONFIG0_TYPE(x)				((x) << 0)
+#define VIVS_TE_SAMPLER_CONFIG0_TYPE(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
-#define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x)			((x) << 3)
+#define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
-#define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x)			((x) << 5)
+#define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
 #define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT			7
-#define VIVS_TE_SAMPLER_CONFIG0_MIN(x)				((x) << 7)
+#define VIVS_TE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
 #define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT			9
-#define VIVS_TE_SAMPLER_CONFIG0_MIP(x)				((x) << 9)
+#define VIVS_TE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
 #define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT			11
-#define VIVS_TE_SAMPLER_CONFIG0_MAG(x)				((x) << 11)
+#define VIVS_TE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
-#define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x)			((x) << 13)
+#define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK)
 
 #define VIVS_TE_SAMPLER_SIZE(i0)			       (0x00002040 + 0x4*(i0))
 #define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
 #define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT			0
-#define VIVS_TE_SAMPLER_SIZE_WIDTH(x)				((x) << 0)
+#define VIVS_TE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK)
 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT			16
-#define VIVS_TE_SAMPLER_SIZE_HEIGHT(x)				((x) << 16)
+#define VIVS_TE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK)
 
 #define VIVS_TE_SAMPLER_LOG_SIZE(i0)			       (0x00002080 + 0x4*(i0))
 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
-#define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x)			((x) << 0)
+#define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK)
 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
-#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x)			((x) << 10)
+#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
 
 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0)			       (0x000020c0 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
-#define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x)			((x) << 1)
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK)
 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
-#define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x)			((x) << 11)
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK)
 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
-#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x)			((x) << 21)
+#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK)
 
 #define VIVS_TE_SAMPLER_UNK02100(i0)			       (0x00002100 + 0x4*(i0))
 
@@ -2919,19 +2938,19 @@ Copyright (C) 2013
 #define VIVS_TE_SAMPLER_CONFIG1(i0)			       (0x000021c0 + 0x4*(i0))
 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000001f
 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
-#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x)			((x) << 0)
+#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK			0x00000700
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
-#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x)			((x) << 8)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK			0x00007000
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
-#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x)			((x) << 12)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK			0x00070000
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
-#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x)			((x) << 16)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK			0x00700000
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
-#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x)			((x) << 20)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
 
 #define VIVS_TE_SAMPLER_UNK02200(i0)			       (0x00002200 + 0x4*(i0))
 
@@ -2950,52 +2969,53 @@ Copyright (C) 2013
 #define VIVS_NTE_SAMPLER_CONFIG0(i0)			       (0x00010000 + 0x4*(i0))
 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT			0
-#define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x)			((x) << 0)
+#define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
-#define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x)			((x) << 3)
+#define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
-#define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x)			((x) << 5)
+#define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT			7
-#define VIVS_NTE_SAMPLER_CONFIG0_MIN(x)				((x) << 7)
+#define VIVS_NTE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT			9
-#define VIVS_NTE_SAMPLER_CONFIG0_MIP(x)				((x) << 9)
+#define VIVS_NTE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT			11
-#define VIVS_NTE_SAMPLER_CONFIG0_MAG(x)				((x) << 11)
+#define VIVS_NTE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
-#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x)			((x) << 13)
+#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK)
 
 #define VIVS_NTE_SAMPLER_SIZE(i0)			       (0x00010080 + 0x4*(i0))
 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT			0
-#define VIVS_NTE_SAMPLER_SIZE_WIDTH(x)				((x) << 0)
+#define VIVS_NTE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK)
 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT			16
-#define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x)				((x) << 16)
+#define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK)
 
 #define VIVS_NTE_SAMPLER_LOG_SIZE(i0)			       (0x00010100 + 0x4*(i0))
 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
-#define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x)			((x) << 0)
+#define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK)
 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
-#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x)			((x) << 10)
+#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
 
 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0)			       (0x00010180 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
-#define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x)			((x) << 1)
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK)
 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
-#define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x)			((x) << 11)
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK)
 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
-#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x)			((x) << 21)
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK)
 
 #define VIVS_NTE_SAMPLER_UNK10200(i0)			       (0x00010200 + 0x4*(i0))
 
@@ -3006,19 +3026,19 @@ Copyright (C) 2013
 #define VIVS_NTE_SAMPLER_CONFIG1(i0)			       (0x00010380 + 0x4*(i0))
 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000001f
 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
-#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x)			((x) << 0)
+#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK		0x00000700
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
-#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x)			((x) << 8)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK		0x00007000
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
-#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x)			((x) << 12)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK		0x00070000
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
-#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x)			((x) << 16)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK		0x00700000
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
-#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x)			((x) << 20)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
 
 #define VIVS_NTE_SAMPLER_UNK10400(i0)			       (0x00010400 + 0x4*(i0))
 
diff --git a/native/resources/test_image-dxt1a.dds b/native/resources/test_image-dxt1a.dds
new file mode 100644
index 0000000..2a8f1b4
--- /dev/null
+++ b/native/resources/test_image-dxt1a.dds
diff --git a/native/resources/test_image-dxt1c.dds b/native/resources/test_image-dxt1c.dds
new file mode 100644
index 0000000..552889e
--- /dev/null
+++ b/native/resources/test_image-dxt1c.dds
diff --git a/native/resources/test_image-dxt3.dds b/native/resources/test_image-dxt3.dds
new file mode 100644
index 0000000..0e26310
--- /dev/null
+++ b/native/resources/test_image-dxt3.dds
diff --git a/rnndb/state.xml b/rnndb/state.xml
index 069de12..aee9c76 100644
--- a/rnndb/state.xml
+++ b/rnndb/state.xml
@@ -335,6 +335,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <value value="7" name="YUY2"/><!-- only supported with YUY2_AVERAGING -->
     </enum>
     <enum name="TEXTURE_FORMAT" brief="Texture format">
+        <!-- 0 read as all zeros -->
         <value value="1" name="A8"/>
         <value value="2" name="L8"/>
         <value value="3" name="I8"/>
@@ -352,10 +353,17 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <value value="15" name="UYVY" brief="YUV 4:2:2 (Alt macropixel ordering)"/>
         <value value="16" name="D16"/>
         <value value="17" name="D24S8"/>
-        <value value="19" name="DXT1" brief="S3 Block Compression 1"/>
+        <!-- 18 reads as all ones -->
+        <value value="19" name="DXT1" brief="S3 Block Compression 1">
+            <doc>DXT1: Unknown tiling.</doc>
+        </value>
         <value value="20" name="DXT2_DXT3" brief="S3 Block Compression 2"/>
-        <value value="21" name="DXT4_DXT5" brief="S3 Block Compression 3"/>
+        <value value="21" name="DXT4_DXT5" brief="S3 Block Compression 3">
+            <doc>DXT4/DXT5 compressed textures are stored untiled.</doc>
+        </value>
+        <!-- 22-29 read as all zeros -->
         <value value="30" name="ETC1" brief="Ericsson Texture Compression"/>
+        <!-- 31 read as all ones -->
     </enum>
     <enum name="TEXTURE_FORMAT_EXT" brief="Extended texture format">
         <value value="0" name="NONE"/>
@@ -373,13 +381,20 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <value value="3" name="ANISOTROPIC"/><!-- Only supported if HALTI0 feature bit set -->
     </enum>
     <enum name="TEXTURE_TYPE">
+        <!-- 0 shows up as black -->
+        <!-- 1 crashes GPU -->
         <value value="2" name="2D"/>
+        <!-- 3 crashes GPU -->
+        <!-- 4 crashes GPU -->
         <value value="5" name="CUBE_MAP"/>
+        <!-- 6 crashes GPU -->
+        <!-- 7 crashes GPU -->
     </enum>
     <enum name="TEXTURE_WRAPMODE">
         <value value="0" name="REPEAT"/>
         <value value="1" name="MIRRORED_REPEAT"/>
         <value value="2" name="CLAMP_TO_EDGE"/>
+        <!-- 3 seems to be same as REPEAT -->
     </enum>
     <enum name="TEXTURE_FACE">
         <doc>Offset into texture memory for cube map face</doc>
@@ -1294,11 +1309,26 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <reg32 offset="0x0080C" name="TEMP_REGISTER_CONTROL" brief="Temporary register control" value="0x00000000">
             <bitfield high="5" low="0" name="NUM_TEMPS" type="uint" brief="Number of temporary registers"/>
         </reg32>
-        <reg32 offset="0x00810" name="OUTPUT" value="0x00000000" length="4" stride="4">
-            <bitfield high="15" low="0" name="UNK0" type="uint"/>
-            <bitfield high="31" low="16" name="UNK16" type="uint"/>
+        <reg32 offset="0x00810" name="OUTPUT" value="0x00000000" brief="Output routing" length="4" stride="4">
+            <doc>
+                Each bitfield (up to 16 in total) contains a temporary register number that 
+                is used as output at the end of the shader for that varying.
+            </doc>
+            <bitfield high="7" low="0" name="O0" type="uint"/>
+            <bitfield high="15" low="8" name="O1" type="uint"/>
+            <bitfield high="23" low="16" name="O2" type="uint"/>
+            <bitfield high="31" low="24" name="O3" type="uint"/>
+        </reg32>
+        <reg32 offset="0x00820" name="INPUT" value="0x00000000" brief="Input routing" length="4" stride="4">
+            <doc>
+                Each bitfield (up to 16 in total) contains a temporary register number that 
+                is assigned the input for that attribute at the beginning of shader execution.
+            </doc>
+            <bitfield high="7" low="0" name="I0" type="uint"/>
+            <bitfield high="15" low="8" name="I1" type="uint"/>
+            <bitfield high="23" low="16" name="I2" type="uint"/>
+            <bitfield high="31" low="24" name="I3" type="uint"/>
         </reg32>
-        <reg32 offset="0x00820" name="INPUT" value="0x00000000" length="4" stride="4"/>
         <reg32 offset="0x00830" name="LOAD_BALANCING" value="0x00000000"/>
         <reg32 offset="0x00834" name="PERF_COUNTER" brief="Performance counter control"/>
         <reg32 offset="0x00838" name="START_PC" value="0x00000000"/>
@@ -1381,7 +1411,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <reg32 offset="0x00A38" name="LINE_UNK00A38" value="0x00000000"/>
         <reg32 offset="0x00A3C" name="LINE_UNK00A3C" value="0x00000000"/>
         <reg32 offset="0x00A40" name="SHADER_ATTRIBUTES" value="0x00000000" length="10" stride="4">
-            <doc>One flags word per shader attribute</doc>
+            <doc>Flags word per shader attribute</doc>
             <bitfield high="7" low="0" name="UNK0"/>
             <bitfield high="15" low="8" name="UNK8"/>
         </reg32>
@@ -1395,8 +1425,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <reg32 offset="0x00C04" name="SCISSOR_TOP" value="0x00000000" type="fixedp"/>
         <reg32 offset="0x00C08" name="SCISSOR_RIGHT" value="0x45000000" type="fixedp"/>
         <reg32 offset="0x00C0C" name="SCISSOR_BOTTOM" value="0x45000000" type="fixedp"/>
-        <reg32 offset="0x00C10" name="DEPTH_SCALE" value="0x00000000"/>
-        <reg32 offset="0x00C14" name="DEPTH_BIAS" value="0x00000000"/>
+        <reg32 offset="0x00C10" name="DEPTH_SCALE" value="0x00000000" type="float"/>
+        <reg32 offset="0x00C14" name="DEPTH_BIAS" value="0x00000000" type="float"/>
         <reg32 offset="0x00C18" name="LAST_PIXEL_ENABLE" value="0x00000000"><doc>Always disabled for OpenGL</doc></reg32>
         <reg32 offset="0x00C1C" name="UNK00C1C" value="0x42000000"/>
         <reg32 offset="0x00C20" name="CLIP_RIGHT" value="0x00000000" type="fixedp"/>
@@ -1798,9 +1828,23 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
         <bitfield high="19" low="10" name="HEIGHT" type="fixedp"/>
     </bitset>
     <bitset name="TE_SAMPLER_LOD_CONFIG" inline="yes">
-        <bitfield high="10" low="1" name="MAX" type="fixedp" brief="Maximum LOD level"/>
-        <bitfield high="20" low="11" name="MIN" type="fixedp" brief="Minimum LOD level"/>
-        <bitfield high="30" low="21" name="BIAS" type="fixedp" brief="LOD bias"/>
+        <bitfield pos="0" name="BIAS_ENABLE" brief="Enable LOD bias"/>
+        <bitfield high="10" low="1" name="MAX" type="fixedp" brief="Maximum LOD level">
+            <doc>
+            This fixed-point value is the maximum LOD level. It can be a fractional value, up to the number of defined mipmaps.
+            </doc>
+        </bitfield>
+        <bitfield high="20" low="11" name="MIN" type="fixedp" brief="Minimum LOD level">
+            <doc>
+            This fixed-point value is the minimum LOD level. It can be a fractional value.
+            </doc>
+        </bitfield>
+        <bitfield high="30" low="21" name="BIAS" type="fixedp" brief="LOD bias">
+            <doc>
+            This fixed-point value is added to the computed LOD level. It appears that it can also be 
+            negative by using two's complement arithmetic.
+            </doc>
+        </bitfield>
     </bitset>
     <bitset name="TE_SAMPLER_CONFIG1" inline="yes">
         <bitfield high="4" low="0" name="FORMAT_EXT" type="TEXTURE_FORMAT_EXT"/>