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| author | Wladimir J. van der Laan <laanwj@gmail.com> | 2013-09-03 13:36:15 +0200 |
|---|---|---|
| committer | Wladimir J. van der Laan <laanwj@gmail.com> | 2013-09-03 13:36:15 +0200 |
| commit | 5b51c9f09928e22aca16014207215805bfa4f342 (patch) | |
| tree | a08adff46fb95db99ae784940e1df02df87e1c94 | |
| parent | 8ef74c1a7b3157f118c77e1698a3c64e95d3a4ef (diff) | |
driver: uncomment set up TS before blit
The code to set up the TS to the source surface before blit should be safe to use now.
Only change TS if it differs from the desired state (so if necessary).
Some flushing may still be needed when changing TS value we'll see
that soon enough.
| -rw-r--r-- | native/driver/etna_screen.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/native/driver/etna_screen.c b/native/driver/etna_screen.c index 797e52f..c929514 100644 --- a/native/driver/etna_screen.c +++ b/native/driver/etna_screen.c @@ -430,23 +430,23 @@ static void etna_screen_flush_frontbuffer( struct pipe_screen *screen, etna_set_state(ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR); etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE); - /* Set up TS before blit */ - /* Could leave the depth bits alone here */ -#if 0 - if(rt_resource->levels[level].ts_address) + /* Set up color TS to source surface before blit, if needed */ + if(rt_resource->levels[level].ts_address != ectx->gpu3d.TS_COLOR_STATUS_BASE) { - etna_set_state_multi(ctx, VIVS_TS_MEM_CONFIG, 4, (uint32_t[]) { - ectx->gpu3d.TS_MEM_CONFIG = VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR, /* XXX |= VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(cbuf->format) */ - ectx->gpu3d.TS_COLOR_STATUS_BASE = rt_resource->levels[level].ts_address, - ectx->gpu3d.TS_COLOR_SURFACE_BASE = rt_resource->levels[level].address, - ectx->gpu3d.TS_COLOR_CLEAR_VALUE = rt_resource->levels[level].clear_value - }); - } else { - etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0x00000000); - ectx->gpu3d.TS_MEM_CONFIG = 0; + if(rt_resource->levels[level].ts_address) + { + etna_set_state_multi(ctx, VIVS_TS_MEM_CONFIG, 4, (uint32_t[]) { + ectx->gpu3d.TS_MEM_CONFIG = VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR, /* XXX |= VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(cbuf->format) */ + ectx->gpu3d.TS_COLOR_STATUS_BASE = rt_resource->levels[level].ts_address, + ectx->gpu3d.TS_COLOR_SURFACE_BASE = rt_resource->levels[level].address, + ectx->gpu3d.TS_COLOR_CLEAR_VALUE = rt_resource->levels[level].clear_value + }); + } else { + etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0x00000000); + ectx->gpu3d.TS_MEM_CONFIG = 0; + } + ectx->dirty_bits |= ETNA_STATE_TS; } - ectx->dirty_bits |= ETNA_STATE_TS; -#endif /* Kick off RS here */ struct compiled_rs_state copy_to_screen; |